Inventor

Haiting Wang

Inventor

Clifton Park, NY, US

Overview

2012–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 80 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices30%

H01LSemiconductor devices29%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%

H10BElectronic memory devices1%

B08BCleaning in general1%

B82YSpecific uses or applications of nanostructures1%

C25DProcesses for the electrolytic or electrophoretic production of coatings1%

B01DSeparation0%

C30BSingle-crystal growth0%

PatentTitleYear

11,008,669Apparatus for holding a substrate2021 11,000,782Method and apparatus for cleaning substrates using high temperature chemicals and ultrasonic device2021 10,910,244Methods and system for cleaning semiconductor wafers2021 10,907,266Method and apparatus for uniformly metallization on substrate2021 10,872,979Spacer structures for a transistor device2020 10,840,245Semiconductor device with reduced parasitic capacitance2020 10,833,169Metal gate for a field effect transistor and method2020 10,832,966Methods and structures for a gate cut2020 10,833,067Metal resistor structure in at least one cavity in dielectric over TS contact and gate structure2020 10,832,839Metal resistors with a non-planar configuration2020 10,832,965Fin reveal forming STI regions having convex shape between fins2020 10,825,913Methods, apparatus, and manufacturing system for FinFET devices with reduced parasitic capacitance2020 10,818,557Integrated circuit structure to reduce soft-fail incidence and method of forming same2020 10,818,659FinFET having upper spacers adjacent gate and source/drain contacts2020 10,818,498Shaped gate caps in spacer-lined openings2020 10,797,049FinFET structure with dielectric bar containing gate to reduce effective capacitance, and method of forming same2020 10,784,143Trench isolation preservation during transistor fabrication2020 10,763,176Transistor with a gate structure comprising a tapered upper surface2020 10,727,133Method of forming gate structure with undercut region and resulting device2020 10,714,376Method of forming semiconductor material in trenches having different widths, and related structures2020 10,707,303Method, apparatus, and system for improving scaling of isolation structures for gate, source, and/or drain contacts2020 10,707,175Asymmetric overlay mark for overlay measurement2020 10,700,173FinFET device with a wrap-around silicide source/drain contact structure2020 10,692,987IC structure with air gap adjacent to gate structure and methods of forming same2020 10,685,881Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a semiconductor device2020 10,651,173Single diffusion cut for gate structures2020 10,636,890Chamfered replacement gate structures2020 10,629,694Gate contact and cross-coupling contact formation2020 10,629,739Methods of forming spacers adjacent gate structures of a transistor device2020 10,600,914Isolation pillar first gate structures and methods of forming same2020 10,593,757Integrated circuits having converted self-aligned epitaxial etch stop2020 10,586,860Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process2020 10,586,736Hybrid fin cut with improved fin profiles2020 10,580,701Methods of making a self-aligned gate contact structure and source/drain metallization structures on integrated circuit products2020 10,580,685Integrated single diffusion break2020 10,535,771Method for forming replacement air gap2020 10,522,410Performing concurrent diffusion break, gate and source/drain contact cut etch processes2019 10,522,644Different upper and lower spacers for contact2019 10,522,538Using source/drain contact cap during gate cut2019 10,475,890Scaled memory structures or other logic devices with middle of the line cuts2019 10,468,481Self-aligned single diffusion break isolation with reduction of strain loss2019 10,431,499Insulating gate separation structure2019 10,403,742Field-effect transistors with fins formed by a damascene-like process2019 10,396,206Gate cut method2019 10,388,652Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same2019 10,373,877Methods of forming source/drain contact structures on integrated circuit products2019 10,373,875Contacts formed with self-aligned cuts2019 10,361,289Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same2019 10,325,811Field-effect transistors with fins having independently-dimensioned sections2019 10,249,616Methods of forming a resistor structure between adjacent transistor gates on an integrated circuit product and the resulting devices2019 10,192,746STI inner spacer to mitigate SDB loading2019 10,164,010Finfet diffusion break having protective liner in fin insulator2018 10,153,209Insulating gate separation structure and methods of making same2018 10,121,788Fin-type field effect transistors with single-diffusion breaks and method2018 10,083,874Gate cut method2018 10,008,385Enlarged sacrificial gate caps for forming self-aligned contacts2018 9,984,933Silicon liner for STI CMP stop in FinFET2018 9,935,104Fin-type field effect transistors with single-diffusion breaks and method2018 9,698,269'Conformal nitridation of one or more fin-type transistor layers'2017 9,653,583'Methods of forming diffusion breaks on integrated circuit products comprised of finFET devices'2017 9,443,771'Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology'2016 9,425,100'Methods of facilitating fabricating transistors'2016 9,418,899'Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and FinFET technology'2016 9,379,186'Fet structure for minimum size length/width devices for performance boost and mismatch reduction'2016 9,331,159'Fabricating transistor(s) with raised active regions having angled upper surfaces'2016 9,312,145'Conformal nitridation of one or more fin-type transistor layers'2016 9,293,580'Lightly doped source/drain last method for dual-epi integration'2016 9,209,258'Depositing an etch stop layer before a dummy cap layer to improve gate performance'2015 9,202,697'Forming a gate by depositing a thin barrier layer on a titanium nitride cap'2015 9,147,572'Using sacrificial oxide layer for gate length tuning and resulting device'2015 9,093,557'Completing middle of line integration allowing for self-aligned contacts'2015 8,952,459'Gate structure having lightly doped region'2015 8,900,940'Reducing gate height variance during semiconductor device formation'2014 8,722,485'Integrated circuits having replacement gate structures and methods for fabricating the same'2014 8,633,070'Lightly doped source/drain last method for dual-epi integration'2014 8,535,998'Method for fabricating a gate structure'2013 8,502,316'Self-aligned two-step STI formation through dummy poly removal'2013 8,405,160'Multi-strained source/drain structures'2013 8,368,147'Strained semiconductor device with recessed channel'2013 8,324,668'Dummy structure for isolating devices in integrated circuits'2012

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2012–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (8)· patent assignee history

2012–2014Patents assigned to WANG HAITING (6)· patent assignee history

2012–2016Based in Hsinchu, TW· patent location history

2013–2014Patents assigned to TSAI HAN-TING (5)· patent assignee history

2014–2020Patents assigned to GLOBALFOUNDRIES INC (68)· patent assignee history

2014–2020Based in Clifton Park, NY, US· patent location history

2021Patents assigned to ACM RESEARCH SHANGHAI INC (4)· patent assignee history

2021Based in Shanghai, CN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
GLOBALFOUNDRIES INC	68	2014–2020
TAIWAN SEMICONDUCTOR MFG	8	2012–2016
WANG HAITINGself	6	2012–2014
TSAI HAN-TING	5	2013–2014
ACM RESEARCH SHANGHAI INC	4	2021

Locations

Location	Patents	Span
Clifton Park, New York, US	68	2014–2020
Hsinchu, TW	8	2012–2016
Shanghai, CN	4	2021