Inventor

Pin-Chin Connie Wang

Inventor

Menlo Park, CA, US

Overview

2001–2010

Patent span

Electricity

Primary field (CPC H)

Patents· 53 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1062%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%

C23CCoating metallic material5%

C25DProcesses for the electrolytic or electrophoretic production of coatings3%

Y10TTechnical subjects covered by former us classification3%

C30BSingle-crystal growth1%

G01NInvestigating or analysing materials by determining their chemical or physical properties1%

H10NElectric solid-state devices not otherwise provided for1%

PatentTitleYear

7,696,092'Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect'2010 7,169,706'Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition'2007 6,992,004'Implanted barrier layer to improve line reliability and method of forming same'2006 6,979,903'Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers'2005 6,939,803'Method for forming conductor reservoir volume for integrated circuit interconnects'2005 6,893,955'Manufacturing seedless barrier layers in integrated circuits'2005 6,861,349'Method of forming an adhesion layer with an element reactive with a barrier layer'2005 6,841,473'Manufacturing an integrated circuit with low solubility metal-conductor interconnect cap'2005 6,833,625'Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect'2004 6,831,003'Continuous barrier for interconnect structure formed in porous dielectric material with minimized electromigration'2004 6,815,340'Method of forming an electroless nucleation layer on a via bottom'2004 6,710,452'Coherent diffusion barriers for integrated circuit interconnects'2004 6,674,170'Barrier metal oxide interconnect cap in integrated circuits'2004 6,663,787'Use of ta/tan for preventing copper contamination of low-k dielectric layers'2003 6,664,185'Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect'2003 6,656,836'Method of performing a two stage anneal in the formation of an alloy interconnect'2003 6,657,303'Integrated circuit with low solubility metal-conductor interconnect cap'2003 6,649,034'Electro-chemical metal alloying for semiconductor manufacturing'2003 6,642,145'Method of manufacturing an integrated circuit with a dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers'2003 6,621,290'Characterization of barrier layers in integrated circuit interconnects'2003 6,617,176'METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING METALLIZATION DIFFUSION BY FORMING A TEST SPECIMEN DEVICE AND USING A METAL PENETRATION MEASUREMENT TECHNIQUE FOR FABRICATING A PRODUCTION SEMICONDUCTOR DEVICE AND A TEST SPECIMEN DEVICE THEREBY FORMED'2003 6,589,408'Non-planar copper alloy target for plasma vapor deposition systems'2003 6,590,288'Selective deposition in integrated circuit interconnects'2003 6,573,179'Forming a strong interface between interconnect and encapsulation to minimize electromigration'2003 6,566,248'Graphoepitaxial conductor cores in integrated circuit interconnects'2003 6,555,909'Seedless barrier layers in integrated circuits and a method of manufacture therefor'2003 6,548,395'Method of promoting void free copper interconnects'2003 6,541,860'Barrier-to-seed layer alloying in integrated circuit interconnects'2003 6,534,865'Method of enhanced fill of vias and trenches'2003 6,531,780'Via formation in integrated circuit interconnects'2003 6,528,412'Depositing an adhesion skin layer and a conformal seed layer to fill an interconnect opening'2003 6,525,425'Copper interconnects with improved electromigration resistance and low resistivity'2003 6,518,185'Integration scheme for non-feature-size dependent cu-alloy introduction'2003 6,518,167'Method of forming a metal or metal nitride interface layer between silicon nitride and copper'2003 6,472,757'Conductor reservoir volume for integrated circuit interconnects'2002 6,469,385'Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers'2002 6,462,416'Gradated barrier layer in integrated circuit interconnects'2002 6,462,417'Coherent alloy diffusion barrier for integrated circuit interconnects'2002 6,455,938'Integrated circuit interconnect shunt layer'2002 6,447,933'Formation of alloy material using alternating depositions of alloy doping element and bulk material'2002 6,445,070'Coherent carbide diffusion barrier for integrated circuit interconnects'2002 6,433,402'Selective copper alloy deposition'2002 6,426,293'Minimizing resistance and electromigration of interconnect by adjusting anneal temperature and amount of seed layer dopant'2002 6,417,566'Void eliminating seed layer and conductor core integrated circuit interconnects'2002 6,417,100'Annealing ambient in integrated circuit interconnects'2002 6,403,474'Controlled anneal conductors for integrated circuit interconnects'2002 6,387,806'Filling an interconnect opening with different types of alloys to enhance interconnect reliability'2002 6,358,840'Forming and filling a recess in interconnect with alloy to minimize electromigration'2002 6,346,479'Method of manufacturing a semiconductor device having copper interconnects'2002 6,309,959'Formation of self-aligned passivation for interconnect to minimize electromigration'2001 6,228,759'Method of forming an alloy precipitate to surround interconnect to minimize electromigration'2001 6,207,552'Forming and filling a recess in interconnect for encapsulation to minimize electromigration'2001 6,190,752'Thin films having rock-salt-like structure deposited on amorphous surfaces'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2007Patents assigned to ADVANCED MICRO DEVICES INC (51)· patent assignee history

2001Patents assigned to UNIV LELAND STANFORD JUNIOR (1)· patent assignee history

2001–2010Based in Menlo Park, CA, US· patent location history

2010Patents assigned to GLOBALFOUNDRIES INC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	51	2001–2007
GLOBALFOUNDRIES INC	1	2010
UNIV LELAND STANFORD JUNIOR	1	2001

Locations

Location	Patents	Span
Menlo Park, California, US	53	2001–2010