Inventor
Chun-Hon Chen
Inventor
Hsinchu, TW
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices41%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1038%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
H01FMagnets3%
PatentTitleYear
7,317,221'High density MIM capacitor structure and fabrication process'20087,294,544'Method of making a metal-insulator-metal capacitor in the CMOS process'20077,122,878'Method to fabricate high reliable metal capacitor within copper back-end process'20067,050,290'Integrated capacitor'20067,035,083'Interdigitated capacitor and method for fabrication thereof'20066,949,781'Metal-over-metal devices and the method for manufacturing same'20056,916,722'Method to fabricate high reliable metal capacitor within copper back-end process'20056,881,996'Metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer'20056,812,088'Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer'20046,734,079'Microelectronic fabrication having sidewall passivated microelectronic capacitor structure fabricated therein'20046,667,217'Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process'20036,583,491'Microelectronic fabrication having microelectronic capacitor structure fabricated therein'20036,472,721'Dual damascene interconnect structures that include radio frequency capacitors and inductors'20026,329,234'Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow'20016,051,475'Method for manufacturing a silicide to silicide capacitor'20005,880,040'Gate dielectric based on oxynitride grown in N.sub.2 O and annealed in NO'19995,874,356'Method for forming zig-zag bordered openings in semiconductor structures'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2008Patents assigned to TAIWAN SEMICONDUCTOR MFG (16)· patent assignee history
1999Patents assigned to MACRONIX INT CO LTD (1)· patent assignee history
1999–2007Based in Hsinchu, TW· patent location history
1999Based in Lung-Jing, TW· patent location history
2000Based in Hsin Chu, TW· patent location history
2005–2006Based in Jhubei City, TW· patent location history
2008Based in Jubei, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 16 | 1999–2008 |
| MACRONIX INT CO LTD | 1 | 1999 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 11 | 1999–2007 |
| Jhubei City, TW | 3 | 2005–2006 |
| Jubei, TW | 1 | 2008 |
| Hsin Chu, TW | 1 | 2000 |
| Lung-Jing, TW | 1 | 1999 |