Inventor
SHAU-LIN SHUE
Inventor
TW
Overview
Patents· 133 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices36%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1036%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10DInorganic electric semiconductor devices10%
B82YSpecific uses or applications of nanostructures2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
C09GPolishing compositions0%
PatentTitleYear
12,581,928Interconnect structure with protective etch-stop202612,564,045Semiconductor device structure with interconnect structure having air gap202612,550,694Selective deposition for integrated circuit interconnect structures202612,543,551Selective formation of conductor nanowires202612,543,550Interconnects including graphene capping and graphene barrier layers202612,538,773Semiconductor structure having self-aligned conductive structure and method for forming the semiconductor structure202612,525,531Protection liner on interconnect wire to enlarge processing window for overlying interconnect via202612,525,538Semiconductor device structure and methods of forming the same202612,512,404Interconnect structure including contact via over barrier layer202512,512,403Method of forming semiconductor device comprising conductive feature, dielectric layer adjacent conductive feature, and etch stop layer on top surface of dielectric layer202512,500,173Interconnect structure with hybrid barrier layer202512,482,703Semiconductor device having thermally conductive air gap structure and method for manufacturing the same202512,482,743Interconnect structure and method for forming the same202512,463,134Semiconductor interconnection structure and methods of forming the same202512,431,386Semiconductor device having metallization layer with low capacitance and method for manufacturing the same202512,412,780Semiconductor device structure and methods of forming the same202512,412,804Semiconductor structure with improved heat dissipation202512,394,633Method of fabricating semiconductor device with reduced trench distortions202512,381,143Self-align via structure by selective deposition202512,381,113Semiconductor device structure having air gap and methods of forming the same202512,374,637Semiconductor packages and methods for forming the same202512,362,233Methods of performing chemical-mechanical polishing process in semiconductor devices202512,347,776Integrated chip with graphene based interconnect202512,342,600Titanium-containing diffusion barrier for CMP removal rate enhancement and contamination reduction202512,327,760Interconnect structures having varied materials202512,315,811Graphene barrier layer for reduced contact resistance202512,308,286Interconnect structures including air gaps202512,278,143Method of providing a workpiece including low resistance interconnect low-resistance interconnect202512,272,623Semiconductor packages and methods for forming the same202512,272,597Semiconductor interconnection structures and methods of forming the same202512,266,565Integrated chip with an etch-stop layer forming a cavity202512,249,555Semiconductor device package including a thermal conductive layer and methods of forming the same202512,230,537Semiconductor device structure having air gap and methods of forming the same202512,230,534Semiconductor device and method of manufacture202512,218,060Integrated chip with graphene based interconnect202512,211,788Hybrid interconnect structure for self aligned via202512,211,740Interconnect structure and methods of forming the same202512,211,799Semiconductor packages and methods for forming the same202512,205,886Hybrid method for forming semiconductor interconnect structure202512,176,246Dielectric capping structure overlying a conductive structure to increase stability202412,165,945Thermal interconnect structure for thermal management of electrical interconnect structure202412,166,026Semiconductor packages and methods for forming the same202412,159,814Semiconductor packages and methods for forming the same202412,142,557Integrated chip having a back-side power rail202412,136,567Fully self-aligned interconnect structure202412,132,000Semiconductor device structure and methods of forming the same202412,113,021Graphene-assisted low-resistance interconnect structures and methods of formation thereof202412,094,848Semiconductor packages and methods for forming the same202412,094,764Interconnect structure and methods of forming the same202412,094,816Semiconductor structure having deep metal line and method for forming the semiconductor structure202412,094,815Semiconductor structure having dielectric-on-dielectric structure and method for forming the semiconductor structure202412,080,593Barrier-less structures202412,074,060Semiconductor device structure and methods of forming the same202412,074,084Heat dispersion layers for double sided interconnect202412,068,193Semiconductor device structure with interconnect structure having air gap202412,068,254Interconnection structure and methods of forming the same202412,068,248Semiconductor interconnection structure and methods of forming the same202412,062,572Semiconductor device having metallization layer with low capacitance and method for manufacturing the same202412,051,683Semiconductor packages and methods for forming the same202412,033,889Semiconductor device structure and methods of forming the same202412,009,301Interconnect structure202412,009,202Using a self-assembly layer to facilitate selective formation of an etching stop layer202412,002,750Interconnect structure202412,002,749Barrier and air-gap scheme for high performance interconnects202411,990,400Capping layer overlying dielectric structure to increase reliability202411,972,975Semiconductor device structure having air gap and method for forming the same202411,967,552Methods of forming interconnect structures in semiconductor fabrication202411,948,834Selective deposition of barrier layer202411,935,783Selective deposition for integrated circuit interconnect structures202411,929,326Method of forming graphene barrier layer in interconnect structure202411,929,258Via connection to a partially filled trench202411,923,243Semiconductor structure having air gaps and method for manufacturing the same202411,923,306Semiconductor structure having air gaps and method for manufacturing the same202411,908,792Semiconductor device comprising cap layer over dielectric layer and method of manufacture202411,908,794Protection liner on interconnect wire to enlarge processing window for overlying interconnect via202411,908,789Selective formation of conductor nanowires202411,901,221Interconnect strucutre with protective etch-stop202411,901,349Semiconductor packages and methods for forming the same202411,894,238Method of fabricating semiconductor device with reduced trench distortions202411,894,266Metal capping layer and methods thereof202411,860,550Multi-metal fill with self-aligned patterning and dielectric with voids202411,854,944Semiconductor packages and methods for forming the same202311,854,987Semiconductor packages with interconnection features in a seal region and methods for forming the same202311,854,963Semiconductor interconnection structure and methods of forming the same202311,854,820Spacer etching process for integrated circuit design202311,848,190Barrier-less structures202311,810,815Dielectric capping structure overlying a conductive structure to increase stability202311,769,695Semiconductor structure including low-resistance interconnect and integrated circuit device having the same202311,764,106Semiconductor device and method of manufacture202311,756,878Self-aligned via structure by selective deposition202311,749,643Semiconductor packages and methods for forming the same202311,742,239Methods of performing chemical-mechanical polishing process in semiconductor devices202311,735,513Integrated chip having a back-side power rail202311,728,264Hybrid interconnect structure for self aligned via202311,721,627Graphene layer for reduced contact resistance202311,715,689Method of forming metal interconnection202311,710,700Graphene-assisted low-resistance interconnect structures and methods of formation thereof202311,670,595Semiconductor device structure and methods of forming the same202311,658,092Thermal interconnect structure for thermal management of electrical interconnect structure202311,652,055Interconnect structure with hybrid barrier layer202311,640,940Methods of forming interconnection structure including conductive graphene layers202311,640,928Heat dispersion layers for double sided interconnect202311,640,924Structure and method for interconnection with self-alignment202311,594,483Semiconductor structure202311,569,124Interconnect structure having an etch stop layer over conductive lines202311,557,511Semiconductor device structure and methods of forming the same202311,545,389Titanium-containing diffusion barrier for CMP removal rate enhancement and contamination reduction202311,538,749Interconnect structure202211,532,552Method and apparatus for forming self-aligned via with selectively deposited etching stop layer202211,527,435Metal capping layer and methods thereof202211,482,447Method of forming an integrated chip having a cavity between metal features202211,482,451Interconnect structures202211,462,470Method of forming graphene and metallic cap and barrier layers for interconnects202211,450,602Hybrid method for forming semiconductor interconnect structure202211,422,475Multi-metal fill with self-aligned patterning and dielectric with voids202211,404,366Hybrid interconnect structure for self aligned via202211,387,113Method of fabricating semiconductor device with reduced trench distortions202211,361,989Method for manufacturing interconnect structures including air gaps202211,361,994Fully self-aligned interconnect structure202211,355,390Interconnect strucutre with protective etch-stop202211,355,430Capping layer overlying dielectric structure to increase reliability202211,335,596Selective deposition for integrated circuit interconnect structures202211,322,395Dielectric capping structure overlying a conductive structure to increase stability202211,309,241Protection liner on interconnect wire to enlarge processing window for overlying interconnect via202211,296,026Semiconductor device and manufacturing method thereof202211,251,073Selective deposition of barrier layer202211,227,833Interconnect structure and method for forming the same202211,222,843Interconnect structure and method for forming the same202211,211,256Method with CMP for metal ion prevention202111,205,618Graphene barrier layer202111,201,106Semiconductor device with conductors embedded in a substrate202111,189,560Semiconductor device comprising etch stop layer over dielectric layer and method of manufacture202111,152,255Methods of performing chemical-mechanical polishing process in semiconductor devices2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (133)· patent assignee history
2021–2026Based in TW· patent location history
2022Patents assigned to TAIWAN SEMICONDUCTOR MFG (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 133 | 2021–2026 |
| TAIWAN SEMICONDUCTOR MFG | 1 | 2022 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 133 | 2021–2026 |