Inventor

Karthikeyan Avudaiyappan

Inventor

Sunnyvale, CA, US

Overview

2009–2021

Patent span

Physics

Primary field (CPC G)

Patents· 43 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing98%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

PatentTitleYear

10,884,739Systems and methods for load canceling in a processor that is connected to an external interconnect fabric2021 10,698,833Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput2020 10,585,804Systems and methods for non-blocking implementation of cache flush instructions2020 10,565,113Methods and systems for managing synonyms in virtually indexed physically tagged caches2020 10,552,334Systems and methods for acquiring data for loads at different access times from hierarchical sources using a load queue as a temporary storage buffer and completing the load early2020 10,402,322Systems and methods for faster read after write forwarding using a virtual address2019 10,346,302Systems and methods for maintaining the coherency of a store coalescing cache and a load cache2019 10,310,987Systems and methods for accessing a unified translation lookaside buffer2019 10,296,432Systems and methods for invasive debug of a processor without processor execution of instructions2019 10,255,187Systems and methods for implementing weak stream software data and instruction prefetching using a hardware data prefetcher2019 10,248,570Methods, systems and apparatus for predicting the way of a set associative cache2019 10,210,101Systems and methods for flushing a cache with modified data2019 10,073,781Systems and methods for invalidating directory of non-home locations ways2018 10,073,780Methods and systems for tracking addresses stored in non-home cache locations2018 10,013,254Systems and methods for load cancelling in a processor that is connected to an external interconnect fabric2018 9,965,414Systems and methods for managing inter-CPU interrupts between multiple CPUs2018 9,946,538Method and apparatus for providing hardware support for self-modifying code2018 9,928,179'Cache replacement policy'2018 9,916,253'Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput'2018 9,904,625'Methods, systems and apparatus for predicting the way of a set associative cache'2018 9,898,412'Methods, systems and apparatus for predicting the way of a set associative cache'2018 9,858,206'Systems and methods for flushing a cache with modified data'2018 9,842,056'Systems and methods for non-blocking implementation of cache flush instructions'2017 9,767,020'Systems and methods for faster read after write forwarding using a virtual address'2017 9,767,038'Systems and methods for accessing a unified translation lookaside buffer'2017 9,740,612'Systems and methods for maintaining the coherency of a store coalescing cache and a load cache'2017 9,720,831'Systems and methods for maintaining the coherency of a store coalescing cache and a load cache'2017 9,720,839'Systems and methods for supporting a plurality of load and store accesses of a cache'2017 9,710,399'Systems and methods for flushing a cache with modified data'2017 9,678,903'Systems and methods for managing inter-CPU interrupts between multiple CPUs'2017 9,678,882'Systems and methods for non-blocking implementation of cache flush instructions'2017 9,665,468'Systems and methods for invasive debug of a processor without processor execution of instructions'2017 9,632,947'Systems and methods for acquiring data for loads at different access times from hierarchical sources using a load queue as a temporary storage buffer and completing the load early'2017 9,619,382'Systems and methods for read request bypassing a last level cache that interfaces with an external fabric'2017 9,454,491'Systems and methods for accessing a unified translation lookaside buffer'2016 9,430,410'Systems and methods for supporting a plurality of load accesses of a cache in a single cycle'2016 9,424,046'Systems and methods for load canceling in a processor that is connected to an external interconnect fabric'2016 9,361,227'Systems and methods for faster read after write forwarding using a virtual address'2016 9,348,754'Systems and methods for implementing weak stream software data and instruction prefetching using a hardware data prefetcher'2016 9,229,873'Systems and methods for supporting a plurality of load and store accesses of a cache'2016 8,930,674'Systems and methods for accessing a unified translation lookaside buffer'2015 8,402,232'Memory utilization tracking'2013 7,574,547'Ring counter based starvation free weighted priority encoded arbiter'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009Based in Santa Clara, CA, US· patent location history

2013–2018Patents assigned to AVUDAIYAPPAN KARTHIKEYAN (8)· patent assignee history

2013Patents assigned to ORACLE AMERICA INC (1)· patent assignee history

2013–2021Based in Sunnyvale, CA, US· patent location history

2015–2018Patents assigned to ABDALLAH MOHAMMAD (7)· patent assignee history

2015–2016Patents assigned to SOFT MACHINES INC (7)· patent assignee history

2017–2021Patents assigned to INTEL CORP (34)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	34	2017–2021
AVUDAIYAPPAN KARTHIKEYANself	8	2013–2018
ABDALLAH MOHAMMAD	7	2015–2018
SOFT MACHINES INC	7	2015–2016
ORACLE AMERICA INC	1	2013

Locations

Location	Patents	Span
Sunnyvale, California, US	42	2013–2021
Santa Clara, California, US	1	2009