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Inventor

Aftab Ahmad

Inventor
Boise, ID, US

Overview

67→
Patents
1988–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 67 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices35%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
H10BElectronic memory devices6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
G01FMeasuring volume, volume flow, mass flow or liquid level3%
G01NInvestigating or analysing materials by determining their chemical or physical properties3%
C04BLime, magnesia2%
G01RMeasuring electric variables2%
G01KMeasuring temperature2%
PatentTitleYear
10,682,385Saffron treatment method for mammalian maladies202010,597,328Lightweight concrete202010,544,587Composite wall panel202010,161,813Energy efficiency measurement system for four-wall structures201810,139,257Multiphase meter calibration system and methods thereof201810,054,500System for determining thermal transmittance and thermal resistance of building walls assemblies under dynamic weather conditions20189,964,533System for measuring multi-phase fluid flow characteristics20189,254,382'Apparatus for transcutaneous electrical stimulation of the tibial nerve'20169,134,160'Online multi-phase flow meter system'20158,869,627'Multi-phase flow metering system'20148,141,379'Hybrid solar air-conditioning system'20127,176,549'Shallow trench isolation using low dielectric constant insulator'20077,071,067'Fabrication of integrated devices using nitrogen implantation'20066,930,363'Barrier in gate stack for improved gate dielectric integrity'20056,858,507'Graded LDD implant process for sub-half-micron MOS devices'20056,831,347'Shallow trench isolation using low dielectric constant insulator'20046,809,395'Isolation structure having trench structures formed on both side of a locos'20046,770,571'Barrier in gate stack for improved gate dielectric integrity'20046,743,979'Bonding pad isolation'20046,664,600'Graded LDD implant process for sub-half-micron MOS devices'20036,660,600'Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors'20036,552,394'Semiconductor transistor devices and structures with halo regions'20036,495,885'Graded LDD implant process for sub-half-micron MOS devices'20026,448,141'Graded LDD implant process for sub-half-micron MOS devices'20026,444,529'Methods of forming integrated circuitry and methods of forming elevated source/drain regions of a field effect transistor'20026,373,114'Barrier in gate stack for improved gate dielectric integrity'20026,346,439'Semiconductor transistor devices and methods for forming semiconductor transistor devices'20026,333,539'Semiconductor transistor devices and methods for forming semiconductor transistor devices'20016,326,250'Semiconductor processing method of fabricating field effect transistors'20016,319,779'Semiconductor transistor devices and methods for forming semiconductor transistor devices'20016,281,092'Method for manufacturing a metal-to-metal capacitor utilizing only one masking step'20016,211,026'Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors'20016,165,827'Semiconductor transistor devices and methods for forming semiconductor transistor devices'20006,159,813'Graded LDD implant process for sub-half-micron MOS devices'20006,150,204'Semiconductor processing method of fabricating field effect transistors'20006,136,637'Method of forming CMOS circuitry including patterning conductive material overlying field isolation oxide'20006,130,137'Method of forming a resistor and integrated circuitry having a resistor construction'20006,107,145'Method for forming a field effect transistor'20006,090,685'Method of forming a LOCOS trench isolation structure'20006,046,472'Graded LDD implant process for sub-half-micron MOS devices'20006,037,639'Fabrication of integrated devices using nitrogen implantation'20005,946,588'Low temperature sub-atmospheric ozone oxidation process for making thin gate oxides'19995,939,761'Method of forming a field effect transistor'19995,940,712'Method of forming a resistor and integrated circuitry having a resistor construction'19995,923,977'Method of forming CMOS circuitry including patterning a layer of conductive material overlying field isolation oxide'19995,923,078'Method of forming a resistor and integrated circuitry having a resistor construction'19995,849,615'Semiconductor processing method of fabricating field effect transistors'19985,830,798'Method for forming a field effect transistor'19985,821,150'Method of forming a resistor and integrated circuitry having a resistor construction'19985,811,329'Method of forming CMOS circuitry including patterning a layer of conductive material overlying field isolation oxide'19985,780,920'Method of forming a resistor and integrated circuitry having a resistor construction'19985,733,809'Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells'19985,719,424'Graded LDD implant process for sub-half-micron MOS devices'19985,716,862'High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS'19985,702,976'Shallow trench isolation using low dielectric constant insulator'19975,668,037'Method of forming a resistor and integrated circuitry having a resistor construction'19975,494,841'Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells'19965,489,546'Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process'19965,483,175'Method for circuits connection for wafer level burning and testing of individual dies on semiconductor wafer'19965,457,400'Semiconductor array having built-in test circuit for wafer level testing'19955,405,791'Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers'19955,382,533'Method of manufacturing small geometry MOS field-effect transistors having improved barrier layer to hot electron injection'19955,338,700'Method of forming a bit line over capacitor array of memory cells'19945,241,266'Built-in test circuit connection for wafer level burnin and testing of individual dies'19935,208,176'Method of fabricating an enhanced dynamic random access memory (DRAM) cell capacitor using multiple polysilicon texturization'19935,024,961'Blanket punchthrough and field-isolation implant for sub-micron N-channel CMOS devices'19914,724,191'Bonded hydrogen conducting solid electrolytes'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1991–2007Patents assigned to MICRON TECHNOLOGY INC (49)· patent assignee history
1991–2007Based in Boise, ID, US· patent location history
1994–1996Patents assigned to MICRON SEMICONDUCTOR INC (4)· patent assignee history
2001–2005Based in Colorado Springs, CO, US· patent location history
2004Based in Lake Oswego, OR, US· patent location history
2012–2020Patents assigned to UNIV KING FAHD PET & MINERALS (9)· patent assignee history
2012–2020Patents assigned to AHMAD AFTAB (3)· patent assignee history
2012–2014Patents assigned to AL-HADHRAMI LUAI M (2)· patent assignee history
2012–2020Based in Dhahran, SA· patent location history
2016–2020Based in Chicago, IL, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC491991–2007
UNIV KING FAHD PET & MINERALS92012–2020
MICRON SEMICONDUCTOR INC41994–1996
AHMAD AFTABself32012–2020
AL-HADHRAMI LUAI M22012–2014
Locations
LocationPatentsSpan
Boise, ID, US471991–2007
Dhahran, SA92012–2020
Colorado Springs, CO, US72001–2005
Chicago, Illinois, US22016–2020
Lake Oswego, OR, US12004