Inventor
Reinhard Mahnkopf
Inventor
Oberhaching, DE
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1027%
H01LSemiconductor devices24%
H10DInorganic electric semiconductor devices12%
B81BMicrostructural devices or systems, e.g. micromechanical devices9%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
G01CMeasuring distances, levels or bearings3%
G01PMeasuring linear or angular speed, acceleration, deceleration, or shock3%
G06FElectric digital data processing3%
H03HImpedance networks, e.g. resonant circuits1%
PatentTitleYear
11,037,855Contoured-on-heat-sink, wrapped printed wiring boards for system-in-package apparatus202111,018,114Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory202110,535,578Semiconductor devices, and a method for forming a semiconductor device202010,403,602Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory201910,301,176Microelectromechanical system (MEMS) on application specific integrated circuit (ASIC)201910,150,668Microelectromechanical system (MEMS) on application specific integrated circuit (ASIC)201810,141,265Bent-bridge semiconductive apparatus20189,888,577'Passive electrical devices with a polymer carrier'20189,856,136'Chip arrangement and method for manufacturing a chip arrangement'20189,663,353'Microelectromechanical system (MEMS) on application specific integrated circuit (ASIC)'20179,564,400'Methods of forming stacked microelectronic dice embedded in a microelectronic substrate'20179,550,670'Stress buffer layer for integrated microelectromechanical systems (MEMS)'20179,373,588'Stacked microelectronic dice embedded in a microelectronic substrate'20169,252,077'Package vias for radio frequency antenna connections'20169,209,143'Die edge side connection'20159,056,763'Stress buffer layer for integrated microelectromechanical systems (MEMS)'20158,907,480'Chip arrangements'20148,415,191'Integrally fabricated micromachine and logic elements'20138,076,738'Integrally fabricated micromachine and logic elements'20118,076,228'Low noise transistor and method of making same'20116,958,282'SOI semiconductor configuration and method of fabricating the same'20056,232,220'Method for fabricating a semiconductor component having a low contact resistance with respect to heavily doped zones'20015,623,155'MOSFET on SOI substrate'19975,587,599'Bipolar transistor and manufacturing method'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2005Patents assigned to SIEMENS AG (3)· patent assignee history
1996–2001Based in Munich, DE· patent location history
2001–2013Patents assigned to INFINEON TECHNOLOGIES AG (4)· patent assignee history
2005Based in München, DE· patent location history
2011–2016Patents assigned to MAHNKOPF REINHARD (5)· patent assignee history
2011–2021Based in Oberhaching, DE· patent location history
2015–2021Patents assigned to INTEL IP CORP (10)· patent assignee history
2015–2019Patents assigned to INTEL CORP (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL IP CORP | 10 | 2015–2021 |
| INTEL CORP | 6 | 2015–2019 |
| MAHNKOPF REINHARDself | 5 | 2011–2016 |
| INFINEON TECHNOLOGIES AG | 4 | 2001–2013 |
| SIEMENS AG | 3 | 1996–2005 |
Locations
| Location | Patents | Span |
|---|---|---|
| Oberhaching, DE | 20 | 2011–2021 |
| Munich, DE | 3 | 1996–2001 |
| München, DE | 1 | 2005 |