Inventor

Paul A. Bunce

Inventor

Poughkeepsie, NY, US

Overview

44→

Patents

2003–2021

Patent span

Physics

Primary field (CPC G)

Patents· 44 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores66%

H03KPulse technique15%

G06FElectric digital data processing8%

G01RMeasuring electric variables3%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%

PatentTitleYear

11,067,627Noise injection circuit2021 10,978,140Random-access memory array memory cell selection2021 10,840,895Fine-grained programmable delay and pulse shaping circuit2020 10,367,507Dynamic decode circuit with active glitch control2019 10,320,388Dynamic decode circuit with active glitch control method2019 10,312,915Dynamic decode circuit with active glitch control method2019 10,312,916Dynamic decode circuit with delayed precharge2019 10,224,933Dynamic decode circuit with active glitch control2019 9,997,218Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation2018 9,977,485Cache array with reduced power consumption2018 9,971,394Cache array with reduced power consumption2018 9,966,958Dynamic decode circuit with active glitch control2018 9,792,967'Managing semiconductor memory array leakage current'2017 9,786,339'Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation'2017 9,761,289'Managing semiconductor memory array leakage current'2017 9,742,408'Dynamic decode circuit with active glitch control'2017 9,583,211'Incorporating bit write capability with column interleave write enable and column redundancy steering'2017 9,355,692'High frequency write through memory device'2016 9,281,025'Write/read priority blocking scheme using parallel static address decode path'2016 9,281,024'Write/read priority blocking scheme using parallel static address decode path'2016 9,070,433'SRAM supply voltage global bitline precharge pulse'2015 8,861,284'Increasing memory operating frequency'2014 8,599,642'Port enable signal generation for gating a memory array device output'2013 8,351,278'Jam latch for latching memory array output data'2013 8,345,497'Internal bypassing of memory array devices'2013 8,345,490'Split voltage level restore and evaluate clock signals for memory address decoding'2013 8,299,833'Programmable control clock circuit including scan mode'2012 7,688,650'Write control method for a memory array configured with multiple memory subarrays'2010 7,471,590'Write control circuitry and method for a memory array configured with multiple memory subarrays'2008 7,299,374'Clock control method and apparatus for a memory array'2007 7,283,417'Write control circuitry and method for a memory array configured with multiple memory subarrays'2007 7,266,737'Method for enabling scan of defective ram prior to repair'2007 7,233,542'Method and apparatus for address generation'2007 7,210,084'Integrated system logic and ABIST data compression for an SRAM directory'2007 7,102,944'Programmable analog control of a bitline evaluation circuit'2006 7,099,203'Circuit and method for writing a binary value to a memory cell'2006 7,088,638'Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays'2006 7,085,173'Write driver circuit for memory array'2006 7,075,855'Memory output timing control circuit with merged functions'2006 7,023,759'System and method for synchronizing memory array signals'2006 7,009,895'Method for skip over redundancy decode with very low overhead'2006 6,822,885'High speed latch and compare function'2004 6,728,912'SOI cell stability test method'2004 6,584,023'System for implementing a column redundancy scheme for arrays with controls that span multiple data bits'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2021Patents assigned to IBM (44)· patent assignee history

2003–2021Based in Poughkeepsie, NY, US· patent location history

2012–2013Patents assigned to BUNCE PAUL A (5)· patent assignee history

2012–2013Patents assigned to DAVIS JOHN D (5)· patent assignee history

2013Patents assigned to HENDERSON DIANA M (4)· patent assignee history

2013Patents assigned to VORA JIGAR J (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	44	2003–2021
BUNCE PAUL Aself	5	2012–2013
DAVIS JOHN D	5	2012–2013
HENDERSON DIANA M	4	2013
VORA JIGAR J	4	2013

Locations

Location	Patents	Span
Poughkeepsie, New York, US	44	2003–2021