Inventor

Aamer Jaleel

Inventor
Northborough, MA, US

Overview

20→
Patents
2010–2020
Patent span
Physics
Primary field (CPC G)

Patents· 20 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing61%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use23%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications6%
G11CStatic stores3%
H03KPulse technique3%
H04LTransmission of digital information, e.g. telegraphic communication3%
PatentTitleYear
10,853,276Executing distributed memory operations using processing elements connected by distributed channels202010,817,425Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads202010,387,319Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features201910,331,583Executing distributed memory operations using processing elements connected by distributed channels201910,284,470Technologies for network device flow lookup management201910,102,134Instruction and logic for run-time evaluation of multiple prefetchers20189,792,212'Virtual shared cache mechanism in a processing device'20179,720,730'Providing an asymmetric multicore processor system transparently to an operating system'20179,710,380'Managing shared cache by multi-core processor'20179,378,021'Instruction and logic for run-time evaluation of multiple prefetchers'20169,286,128'Processor scheduling with thread performance estimation on cores of different types'20169,262,327'Signature based hit-predicting cache'20168,839,259'Thread scheduling on multiprocessor systems'20148,769,209'Method and apparatus for achieving non-inclusive cache performance with inclusive caches'20148,769,201'Technique for controlling computing resources'20148,533,422'Instruction prefetching using cache line history'20138,407,421'Cache spill management techniques using cache spill prediction'20138,347,301'Device, system, and method of scheduling tasks of a multithreaded application'20138,132,172'Thread scheduling on multiprocessor systems'20127,725,657'Dynamic quality of service (QoS) for a shared cache'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2020Patents assigned to INTEL CORP (20)· patent assignee history
2010–2017Based in Hudson, MA, US· patent location history
2012–2017Patents assigned to JALEEL AAMER (10)· patent assignee history
2012–2014Patents assigned to LI WENLONG (3)· patent assignee history
2013–2016Patents assigned to STEELY JR SIMON C (4)· patent assignee history
2013–2016Based in Cambridge, MA, US· patent location history
2014–2016Patents assigned to EMER JOEL S (2)· patent assignee history
2016–2020Based in Northborough, MA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP202010–2020
JALEEL AAMERself102012–2017
STEELY JR SIMON C42013–2016
LI WENLONG32012–2014
EMER JOEL S22014–2016
Locations
LocationPatentsSpan
Northborough, Massachusetts, US92016–2020
Hudson, Massachusetts, US72010–2017
Cambridge, Massachusetts, US42013–2016