Inventor
Huajun Wen
Inventor
Austin, TX, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing38%
H03KPulse technique21%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use17%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications10%
B82YSpecific uses or applications of nanostructures3%
G01QScanning-probe techniques or apparatus3%
G05FSystems for regulating electric or magnetic variables3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
10,345,882Dynamic power meter with improved accuracy and single cycle resolution20199,146,772'Reducing power grid noise in a processor while minimizing performance loss'20159,141,421'Reducing power grid noise in a processor while minimizing performance loss'20159,052,905'Minimizing power consumption for fixed-frequency processing unit operation'20158,943,341'Minimizing power consumption for fixed-frequency processing unit operation'20158,812,879'Processor voltage regulation'20148,180,815'Redundancy-free circuits for zero counters'20127,461,110'Redundancy-free circuits for zero counters'20087,206,802'Hybrid carry look ahead/carry select adder including carry logic generating complementary hot carry signals, and method for producing the carry logic'20077,024,647'System and method for designing a circuit wherein a single timing analysis ensures adequate performance in multiple applications'20066,718,420'Phase manipulation of intertwined bus signals for reduction of hostile coupling in integrated circuit interconnects'20046,664,836'Dynamic phase splitter circuit and method for low-noise and simultaneous production of true and complement dynamic logic signals'20036,492,856'Edge triggered latch with symmetrical paths from clock to data outputs'20026,445,217'Edge-triggered latch with balanced pass-transistor logic trigger'20026,437,624'Edge-triggered latch with symmetric complementary pass-transistor logic data path'20026,437,625'Edge triggered latch with symmetrical paths from clock to data outputs'20026,407,574'Method and system for utilizing hostile-switching neighbors to improve interconnect speed for high performance processors'20026,085,580'Differential force microscope'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2015Patents assigned to IBM (17)· patent assignee history
2000–2019Based in Austin, TX, US· patent location history
2014–2015Patents assigned to WEN HUAJUN (3)· patent assignee history
2015Patents assigned to ALLEN-WARE MALCOLM S (2)· patent assignee history
2015Patents assigned to DRAKE ALAN J (2)· patent assignee history
2015Patents assigned to FLOYD MICHAEL S (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 17 | 2000–2015 |
| WEN HUAJUNself | 3 | 2014–2015 |
| ALLEN-WARE MALCOLM S | 2 | 2015 |
| DRAKE ALAN J | 2 | 2015 |
| FLOYD MICHAEL S | 2 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 18 | 2000–2019 |