Inventor
CHANG-MIAO LIU
Inventor
TW
Overview
Patents· 53 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices29%
H01LSemiconductor devices24%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
B82YSpecific uses or applications of nanostructures15%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10BElectronic memory devices2%
H10NElectric solid-state devices not otherwise provided for2%
PatentTitleYear
12,575,134Multi-gate devices with reduced contact resistance and methods of forming the same202612,550,358Method of forming transistors of different configurations202612,527,050Integrated circuit structure with source/drain spacers202612,513,979Semiconductor device202512,453,154Dielectric constant reduction of gate spacer202512,414,330Multi-gate device including semiconductor fin between dielectric fins and method of fabrication thereof202512,414,331Isolation for multigate devices202512,389,653Semiconductor devices and methods of fabricating the same202512,363,935Methods for forming multi-gate transistors202512,356,703Air spacer formation for semiconductor devices202512,349,384Isolation structures in multi-gate semiconductor devices and methods of fabricating the same202512,349,432Enlarged backside contact202512,324,218Semiconductor devices with air gaps and the method thereof202512,317,550Methods of forming a semiconductor device with corner isolation protection202512,278,276Multi-channel devices and method with anti-punch through process202512,230,720Semiconductor structure with recessed top semiconductor layer in substrate and method of fabricating the same202512,218,013Gate structures for semiconductor devices202512,183,806Semiconductor devices and methods of fabricating the same202412,166,071Dielectric fins with air gap and backside self-aligned contact202412,166,075Method and structure for gate-all-around devices202412,132,096Semiconductor device structure with metal gate stack202412,113,118Stress-inducing silicon liner in semiconductor devices202412,100,625Semiconductor device with air gaps between metal gates and method of forming the same202412,062,707Method of manufacturing a field effect transistor by tilted implantation of dopants into inner sidewalls of gate spacers202412,015,055Doping for semiconductor device with conductive feature202411,991,936Method of forming a FinFET device202411,973,128Methods for forming multi-gate transistors202411,948,998Isolation structures in multi-gate semiconductor devices and methods of fabricating the same202411,935,954Semiconductor device structure and method for forming the same202411,916,105Semiconductor device with corner isolation protection and methods of forming the same202411,854,906Gate structures for semiconductor devices202311,855,155Semiconductor device having contact feature and method of fabricating the same202311,837,631Source/drain spacer with air gap in semiconductor devices and methods of fabricating the same202311,837,662Devices with strained isolation features202311,769,819Semiconductor device structure with metal gate stack202311,756,835Semiconductor device with air gaps between metal gates and method of forming the same202311,742,386Doping for semiconductor device with conductive feature202311,728,405Stress-inducing silicon liner in semiconductor devices202311,715,803Method of forming transistors of different configurations202311,688,647Semiconductor device and method for manufacturing the same202311,688,768Integrated circuit structure with source/drain spacers202311,600,695Dielectric fins with air gap and backside self-aligned contact202311,594,680Method of forming a FinFET device202311,527,444Air spacer formation for semiconductor devices202211,450,741Doping for semiconductor device with conductive feature202211,444,179Isolation structures in multi-gate semiconductor devices and methods of fabricating the same202211,430,890Integrated circuits with channel-strain liner202211,387,146Semiconductor device with air gaps between metal gates and method of forming the same202211,362,217Method of forming transistors of different configurations202211,355,615FinFET having fluorine-doped gate sidewall spacers202211,302,784Semiconductor device having contact feature and method of fabricating the same202211,145,650Gate cut dielectric feature and method of forming the same202111,139,432Methods of forming a FinFET device2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (53)· patent assignee history
2021–2026Based in TW· patent location history
2025Patents assigned to TAIWAN SEMICONDUCTOR MANUFACTUIRNG CO LTD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 53 | 2021–2026 |
| TAIWAN SEMICONDUCTOR MANUFACTUIRNG CO LTD | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 53 | 2021–2026 |