LexDanaLexDanabeta
Inventor

Kuang-Chao Chen

Inventor
Hsinchu, TW

Overview

67→
Patents
1993–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 67 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H10DInorganic electric semiconductor devices14%
H10BElectronic memory devices9%
H01LSemiconductor devices6%
H01JElectric discharge tubes or discharge lamps3%
G01NInvestigating or analysing materials by determining their chemical or physical properties3%
A61NElectrotherapy2%
G01RMeasuring electric variables2%
G06FElectric digital data processing2%
PatentTitleYear
10,607,848Method of fabricating semiconductor device202010,497,652Semiconductor substrate and semiconductor device201910,413,727Hearing auxiliary device and hearing auxiliary processing method201910,388,664Integrated circuit device with layered trench conductors20199,953,841Semiconductor device and method of fabricating the same20189,901,736'Cochlea hearing aid fixed on eardrum'20189,869,712'Method and system for detecting defects of wafer by wafer sort'20189,656,073'External electronic ear device and cochlear implant device'20179,589,086'Method for measuring and analyzing surface structure of chip or wafer'20179,349,746'Method of fabricating deep trench semiconductor devices, and deep trench semiconductor devices'20169,244,112'Method for detecting an electrical defect of contact/via plugs'20169,116,108'Electron beam inspection optimization'20159,059,094'Semiconductor gate structure and method of fabricating thereof'20159,006,003'Method of detecting bitmap failure associated with physical coordinate'20158,828,861'Method for fabricating conductive lines of a semiconductor device'20148,735,958'Multi-layer polysilicon suppression of implant species penetration'20148,669,184'Method for improving flatness of a layer deposited on polycrystalline layer'20148,653,592'Isolation structure, non-volatile memory having the same, and method of fabricating the same'20148,607,171'System and method for optical proximity correction of a modified integrated circuit layout'20138,594,963'In-line inspection yield prediction system'20138,580,680'Metal silicide formation'20138,520,194'Method of forming a deposited material by utilizing a multi-step deposition/etch/deposition (D/E/D) process'20138,519,541'Semiconductor device having plural conductive layers disposed within dielectric layer'20138,445,346'Method of reducing wordline shorting'20138,383,515'Methodology for wordline short reduction'20138,184,288'Method of depositing a silicon-containing material by utilizing a multi-step fill-in process in a deposition machine'20128,085,390'Multivariate monitoring method for plasma process machine'20118,067,292'Isolation structure, non-volatile memory having the same, and method of fabricating the same'20118,047,899'Pad and method for chemical mechanical polishing'20118,034,691'HDP-CVD process, filling-in process utilizing HDP-CVD, and HDP-CVD system'20118,003,519'Systems and methods for back end of line processing of semiconductor circuits'20117,951,707'Etching method for semiconductor element'20117,938,972'Fabrication method of electronic device'20117,888,804'Method for forming self-aligned contacts and local interconnects simultaneously'20117,846,835'Contact barrier layer deposition process'20107,763,517'Method of forming non-volatile memory cell'20107,629,265'Cleaning method for use in semiconductor device fabrication'20097,625,819'Interconnection process'20097,553,755'Method for symmetric deposition of metal layer'20097,531,411'Apparatus and method for a non-volatile memory structure comprising a multi-layer silicon-rich, silicon nitride trapping layer'20097,517,780'Method for eliminating polycide voids through nitrogen implantation'20097,498,257'Methods for metal ARC layer formation'20097,382,054'Method for forming self-aligned contacts and local interconnects simultaneously'20087,335,610'Ultraviolet blocking layer'20087,045,419'Elimination of the fast-erase phenomena in flash memory'20066,943,118'Method of fabricating flash memory'20056,911,374'Fabrication method for shallow trench isolation region'20056,887,757'Method of manufacturing flash memory'20056,855,617'Method of filling intervals and fabricating shallow trench isolation structures'20056,824,452'Polishing pad and process of chemical mechanical use thereof'20046,812,096'Method for fabrication a flash memory device having self-aligned contact'20046,677,255'Method for removing fences without reduction of ONO film thickness'20046,136,688'High stress oxide to eliminate BPSG/SiN cracking'20006,117,755'Method for planarizing the interface of polysilicon and silicide in a polycide structure'20006,001,745'Method for forming a VIA in an inter metal dielectric (IMD) containing spin on glass (SOG)'19995,989,971'Method for forming trenched polysilicon structure'19995,960,279'Method of fabricating a capacitor on a rugged stacked oxide layer'19995,883,015'Method for using oxygen plasma treatment on a dielectric layer'19995,869,399'Method for increasing utilizable surface of rugged polysilicon layer in semiconductor device'19995,869,394'Teos-ozone planarization process'19995,851,867'Rugged stacked oxide layer structure and method of fabricating same'19985,811,344'Method of forming a capacitor of a dram cell'19985,393,708'Inter-metal-dielectric planarization process'19955,366,850'Submicron planarization process with passivation on metal line'19945,356,836'Aluminum plug process'19945,286,675'Blanket tungsten etchback process using disposable spin-on-glass'19945,250,472'Spin-on-glass integration planarization having siloxane partial etchback and silicate processes'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2019Based in Taipei, TW· patent location history
1998–2000Patents assigned to MOSEL VITELIC INC (6)· patent assignee history
1998–2020Based in Hsinchu, TW· patent location history
2000Based in Chutung, TW· patent location history
2004–2020Patents assigned to MACRONIX INT CO LTD (48)· patent assignee history
2009–2014Based in Hsinchu County, TW· patent location history
2011–2017Patents assigned to CHEN KUANG-CHAO (14)· patent assignee history
2011–2014Patents assigned to LUOH TUUNG (11)· patent assignee history
2011–2014Patents assigned to SU CHIN-TA (8)· patent assignee history
2017–2019Based in New Taipei, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MACRONIX INT CO LTD482004–2020
CHEN KUANG-CHAOself142011–2017
LUOH TUUNG112011–2014
SU CHIN-TA82011–2014
MOSEL VITELIC INC61998–2000
Locations
LocationPatentsSpan
Hsinchu, TW411998–2020
Taipei, TW181993–2019
Hsinchu County, TW42009–2014
New Taipei, TW32017–2019
Chutung, TW12000