Inventor
Mike F. Chang
Inventor
Cupertino, CA, US
Overview
Patents· 68 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices38%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1023%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
C30BSingle-crystal growth6%
B08BCleaning in general1%
G01RMeasuring electric variables1%
H01LSemiconductor devices1%
PatentTitleYear
9,040,356'Semiconductor including cup-shaped leadframe packaging techniques'20158,169,062'Integrated circuit package for semiconductior devices with improved electric resistance and inductance'20128,067,822'Integrated circuit package for semiconductor devices with improved electric resistance and inductance'20117,863,995'Methods of achieving linear capacitance in symmetrical and asymmetrical EMI filters with TVS'20117,633,140'Inverted J-lead for power devices'20097,595,547'Semiconductor die package including cup-shaped leadframe'20097,391,100'Integrated circuit package for semiconductor devices having a reduced leadframe pad and an increased bonding area'20087,208,818'Power semiconductor package'20076,909,170'Semiconductor assembly with package using cup-shaped lead-frame'20056,841,852'Integrated circuit package for semiconductor devices with improved electric resistance and inductance'20056,744,124'Semiconductor die package including cup-shaped leadframe'20046,509,233'Method of making trench-gated MOSFET having cesium gate oxide layer'20036,444,527'Method of operation of punch-through field effect transistor'20026,277,695'Method of forming vertical planar DMOSFET with self-aligned contact'20016,090,716'Method of fabricating a field effect transistor'20006,069,043'Method of making punch-through field effect transistor'20005,998,834'Long channel trench-gated power MOSFET having fully depleted body region'19995,981,344'Trench field effect transistor with reduced punch-through susceptibility and low R.sub.DSon'19995,929,481'High density trench DMOS transistor with trench bottom implant'19995,923,979'Planar DMOS transistor fabricated by a three mask process'19995,917,216'Trenched field effect transistor with PN depletion barrier'19995,910,669'Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof'19995,821,583'Trenched DMOS transistor with lightly doped tub'19985,770,503'Method of forming low threshold voltage vertical power transistor using epitaxial technology'19985,767,578'Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation'19985,757,081'Surface mount and flip chip technology for total integrated circuit isolation'19985,753,529'Surface mount and flip chip technology for total integrated circuit isolation'19985,750,416'Method of forming a lateral field effect transistor having reduced drain-to-source on-resistance'19985,689,128'High density trenched DMOS transistor'19975,639,676'Trenched DMOS transistor fabrication having thick termination region oxide'19975,629,543'Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness'19975,592,005'Punch-through field effect transistor'19975,578,851'Trenched DMOS transistor having thick field oxide in termination region'19965,558,313'Trench field effect transistor with reduced punch-through susceptibility and low R.sub.DSon'19965,532,179'Method of making a field effect trench transistor having lightly doped epitaxial region on the surface portion thereof'19965,521,409'Structure of power mosfets, including termination structures'19965,486,772'Reliability test method for semiconductor trench devices'19965,479,037'Low threshold voltage epitaxial DMOS technology'19955,474,943'Method for fabricating a short channel trenched DMOS transistor'19955,468,982'Trenched DMOS transistor with channel block at cell trench corners'19955,439,842'Low temperature oxide layer over field implant mask'19955,429,964'Low on-resistance power MOS technology'19955,426,325'Metal crossover in high voltage IC with graduated doping control'19955,404,040'Structure and fabrication of power MOSFETs, including termination structures'19955,374,843'Lightly-doped drain MOSFET with improved breakdown characteristics'19945,341,011'Short channel trenched DMOS transistor'19945,328,866'Low temperature oxide layer over field implant mask'19945,316,959'Trenched DMOS transistor fabrication using six masks'19945,304,831'Low on-resistance power MOS technology'19945,132,753'Optimization of BV and RDS-on by graded doping in LDD and other high voltage ICs'19924,883,767'Method of fabricating self aligned semiconductor devices'19894,810,665'Semiconductor device and method of fabrication'19894,803,533'IGT and MOSFET devices having reduced channel width'19894,795,716'Method of making a power IC structure with enhancement and/or CMOS logic'19894,239,560'Open tube aluminum oxide disc diffusion'19804,235,650'Open tube aluminum diffusion'19804,233,934'Guard ring for TGZM processing'19804,188,245'Selective open tube aluminum diffusion'19804,168,992'Process for thermal gradient zone melting utilizing a beveled wafer and a beveled guard ring'19794,159,215'Droplet migration doping using reactive carriers and dopants'19794,108,685'Semiconductor device manufacture'19784,076,559'Temperature gradient zone melting through an oxide layer'19784,042,448'Post TGZM surface etch'19774,040,868'Semiconductor device manufacture'19774,021,269'Post diffusion after temperature gradient zone melting'19774,006,040'Semiconductor device manufacture'19773,998,661'Uniform migration of an annular shaped molten zone through a solid body'19763,998,653'Method for cleaning semiconductor devices'1976Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1976–1989Patents assigned to GEN ELECTRIC (18)· patent assignee history
1976–1989Based in Liverpool, NY, US· patent location history
1989Based in Cary, NC, US· patent location history
1992–2005Patents assigned to SILICONIX INC (39)· patent assignee history
1992–2015Based in Cupertino, CA, US· patent location history
1994–1995Based in Santa Clara, CA, US· patent location history
2005Based in Sunnyvale, CA, US· patent location history
2007–2012Patents assigned to ALPHA & OMEGA SEMICONDUCTOR (6)· patent assignee history
2011–2015Patents assigned to CHANG MIKE (3)· patent assignee history
2011–2015Patents assigned to HO YUEH-SE (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SILICONIX INC | 39 | 1992–2005 |
| GEN ELECTRIC | 18 | 1976–1989 |
| ALPHA & OMEGA SEMICONDUCTOR | 6 | 2007–2012 |
| CHANG MIKEself | 3 | 2011–2015 |
| HO YUEH-SE | 3 | 2011–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 47 | 1992–2015 |
| Liverpool, New York, US | 15 | 1976–1989 |
| Cary, NC, US | 3 | 1989 |
| Santa Clara, California, US | 2 | 1994–1995 |
| Sunnyvale, California, US | 1 | 2005 |