Inventor
Luigi Ternullo, Jr.
Inventor
Colchester, VT, US
Overview
Patents· 30 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores41%
G06FElectric digital data processing16%
G01RMeasuring electric variables14%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems6%
H10BElectronic memory devices6%
H10DInorganic electric semiconductor devices6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
H03KPulse technique4%
C25DProcesses for the electrolytic or electrophoretic production of coatings2%
PatentTitleYear
7,102,421'Dynamically adjustable on-chip supply voltage generation'20066,353,903'Method and apparatus for testing differential signals'20026,327,215'Local bit switch decode circuit and method'20016,246,619'Self-refresh test time reduction scheme'20016,208,197'Internal charge pump voltage limit control'20016,133,748'Crow-bar current reduction circuit'20006,111,447'Timing circuit that selectively triggers on a rising or falling input signal edge'20006,060,873'On-chip-generated supply voltage regulator with power-up mode'20006,061,296'Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices'20006,052,328'High-speed synchronous write control scheme'20006,016,072'Regulator system for an on-chip supply voltage generator'20005,996,097'Testing logic associated with numerous memory cells in the word or bit dimension in parallel'19995,973,895'Method and circuit for disabling a two-phase charge pump'19995,954,830'Method and apparatus for achieving higher performance data compression in ABIST testing by reducing the number of data outputs'19995,796,745'Memory array built-in self test circuit for testing multi-port memory arrays'19985,796,665'Semiconductor memory device with improved read signal generation of data lines and assisted precharge to mid-level'19985,790,564'Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor'19985,784,323'Test converage of embedded memories on semiconductor substrates'19985,771,242'Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor'19985,761,213'Method and apparatus to determine erroneous value in memory cells using data compression'19985,757,050'Field effect transistor having contact layer of transistor gate electrode material'19985,745,498'Rapid compare of two binary numbers'19985,744,384'Semiconductor structures which incorporate thin film transistors'19985,740,098'Using one memory to supply addresses to an associated memory during testing'19985,670,812'Field effect transistor having contact layer of transistor gate electrode material'19975,582,703'Method of fabricating an ultra-high resolution three-color screen'19965,563,833'Using one memory to supply addresses to an associated memory during testing'19965,553,082'Built-in self-test for logic circuitry at memory array output'19965,539,753'Method and apparatus for output deselecting of data during test'19965,535,164'BIST tester for multiple memories'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2002Patents assigned to IBM (17)· patent assignee history
1996Patents assigned to PALOMAR TECHN CORP (1)· patent assignee history
1996–2002Based in Colchester, VT, US· patent location history
1998–2006Patents assigned to VANGUARD INT SEMICONDUCT CORP (12)· patent assignee history
1998–2006Based in San Jose, CA, US· patent location history
1998Based in Golchester, VT, US· patent location history
2001Based in Allentown, PA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 17 | 1996–2002 |
| VANGUARD INT SEMICONDUCT CORP | 12 | 1998–2006 |
| PALOMAR TECHN CORP | 1 | 1996 |
Locations
| Location | Patents | Span |
|---|---|---|
| Colchester, VT, US | 15 | 1996–2002 |
| San Jose, California, US | 13 | 1998–2006 |
| Allentown, Pennsylvania, US | 1 | 2001 |
| Golchester, VT, US | 1 | 1998 |