Inventor
Po-Chao Tsao
Inventor
New Taipei, TW
Overview
Patents· 67 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices32%
H01LSemiconductor devices27%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H10BElectronic memory devices3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
G06FElectric digital data processing1%
G11CStatic stores1%
PatentTitleYear
10,049,929Method of making semiconductor structure having contact plug20189,847,331Semiconductor integrated circuit20179,548,302'Semiconductor integrated circuit'20179,530,862'Semiconductor device having metal gate and manufacturing method thereof'20169,455,176'Manufacturing method for forming semiconductor structure with sub-fin structures'20169,449,964'Semiconductor process'20169,349,695'Semiconductor integrated device including FinFET device and protecting structure'20169,337,260'Shallow trench isolation in bulk substrate'20169,330,980'Semiconductor process'20169,318,490'Semiconductor structure and manufacturing method thereof'20169,318,571'Gate structure and method for trimming spacers'20169,312,359'Semiconductor structure and fabrication method thereof'20169,306,032'Method of forming self-aligned metal gate structure in a replacement gate process using tapered interlayer dielectric'20169,299,843'Semiconductor structure and manufacturing method thereof'20169,281,199'Method for fabricating semiconductor device with paterned hard mask'20169,281,367'Semiconductor structure having contact plug and method of making the same'20169,263,287'Method of forming fin-shaped structure'20169,240,403'Embedded resistor'20169,208,276'Method for generating layout pattern'20159,196,352'Static random access memory unit cell structure and static random access memory unit cell layout structure'20159,196,500'Method for manufacturing semiconductor structures'20159,196,542'Method for manufacturing semiconductor devices'20159,190,497'Method for fabricating semiconductor device with loop-shaped fin'20159,190,291'Fin-shaped structure forming process'20159,159,798'Replacement gate process and device manufactured using the same'20159,147,612'Method for forming a semiconductor structure'20159,141,744'Method for generating layout pattern'20159,136,348'Semiconductor structure and fabrication method thereof'20159,129,985'Semiconductor device having metal gate and manufacturing method thereof'20159,123,810'Semiconductor integrated device including FinFET device and protecting structure'20159,117,925'Epitaxial process'20159,093,473'Method for fabricating metal-oxide semiconductor transistor'20159,093,285'Semiconductor structure and process thereof'20159,064,931'Semiconductor structure having contact plug and metal gate transistor and method of making the same'20159,054,172'Semiconductor structure having contact plug and method of making the same'20159,048,246'Die seal ring and method of forming the same'20159,035,425'Semiconductor integrated circuit'20159,013,003'Semiconductor structure and process thereof'20159,006,072'Method of forming metal silicide layer'20159,006,804'Semiconductor device and fabrication method thereof'20159,000,483'Semiconductor device with fin structure and fabrication method thereof'20158,981,487'Fin-shaped field-effect transistor (FinFET)'20158,951,918'Method for fabricating patterned structure of semiconductor device'20158,928,112'Shallow trench isolation'20158,921,226'Method of forming semiconductor structure having contact plug'20148,912,074'Method of forming shallow trench isolations'20148,883,621'Semiconductor structure and method of fabricating MOS device'20148,860,181'Thin film resistor structure'20148,836,129'Plug structure'20148,823,132'Two-portion shallow-trench isolation'20148,816,409'Metal-oxide semiconductor transistor'20148,592,322'Method of fabricating openings'20138,575,034'Fabricating method of semiconductor element'20138,569,127'Semiconductor device and method for fabricating the same'20138,546,962'Mark structure and method for measuring alignment accuracy between former layer and latter layer'20138,461,649'Opening structure for semiconductor device'20138,236,702'Method of fabricating openings and contact holes'20128,164,141'Opening structure with sidewall of an opening covered with a dielectric thin film'20128,129,235'Method of fabricating two-step self-aligned contact'20127,825,034'Method of fabricating openings and contact holes'20107,817,265'Alignment mark and defect inspection method'20107,759,742'Metal oxide semiconductor transistor'20107,595,234'Fabricating method for a metal oxide semiconductor transistor'20097,572,722'Method of fabricating nickel silicide'20097,384,853'Method of performing salicide processes on MOS transistors'20087,385,294'Semiconductor device having nickel silicide and method of fabricating nickel silicide'20087,214,988'Metal oxide semiconductor transistor'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2018Patents assigned to UNITED MICROELECTRONICS CORP (66)· patent assignee history
2007–2016Based in Taipei, TW· patent location history
2012–2016Patents assigned to TSAO PO-CHAO (12)· patent assignee history
2012–2016Patents assigned to CHEN MING-TSUNG (7)· patent assignee history
2012–2013Patents assigned to CHANG FENG-YI (4)· patent assignee history
2013–2015Patents assigned to WEI MING-TE (6)· patent assignee history
2013–2018Based in New Taipei, TW· patent location history
2013Based in Tainan, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNITED MICROELECTRONICS CORP | 66 | 2007–2018 |
| TSAO PO-CHAOself | 12 | 2012–2016 |
| CHEN MING-TSUNG | 7 | 2012–2016 |
| WEI MING-TE | 6 | 2013–2015 |
| CHANG FENG-YI | 4 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| New Taipei, TW | 52 | 2013–2018 |
| Taipei, TW | 13 | 2007–2016 |
| Tainan, TW | 2 | 2013 |