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Inventor

Kazutaka Nogami

Inventor
Tokyo, JP

Overview

33→
Patents
1988–2004
Patent span
Physics
Primary field (CPC G)

Patents· 33 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores40%
H03KPulse technique23%
G06FElectric digital data processing8%
G05FSystems for regulating electric or magnetic variables4%
H03DDemodulation or transference of modulation from one carrier to another4%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses4%
H10BElectronic memory devices4%
H10DInorganic electric semiconductor devices4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H04LTransmission of digital information, e.g. telegraphic communication2%
PatentTitleYear
6,774,679'Semiconductor integrated circuit'20046,374,281'Adder'20026,215,344'Data transmission circuit'20015,986,309'Semiconductor integrated circuit apparatus having a plurality of well bias voltage supply circuits'19995,860,145'Address translation device storage last address translation in register separate from TLB'19995,809,326'Signal processor and method of operating a signal processor'19985,764,588'Memory circuit'19985,748,011'Output buffer circuit'19985,717,890'Method for processing data by utilizing hierarchical cache memories and processing system with the hierarchiacal cache memories'19985,592,010'Semiconductor device'19975,577,086'Clock signal generation circuit capable of operating at high speed with high frequency'19965,539,331'Field programmable gate array having transmission gates and semiconductor integrated circuit for programming connection of wires'19965,498,978'Field programmable gate array'19965,488,326'Data output circuit for semiconductor integrated circuit device which prevents current flow from the output to supply voltage'19965,479,374'Semiconductor memory device employing sense amplifier control circuit and word line control circuit'19955,459,342'Field programmable gate array with spare circuit block'19955,430,391'Data input/output control circuit'19955,406,511'Mask ROM for storing plural-bit data'19955,388,104'Semiconductor integrated circuit capable of testing memory blocks'19955,379,246'Semiconductor memory device having loop configuration'19955,267,192'Semiconductor memory device'19935,241,510'Semiconductor integrated circuit'19935,175,604'Field-effect transistor device'19925,073,873'Semiconductor memory device'19914,984,208'Dynamic read/write memory with improved refreshing operation'19914,973,864'Sense circuit for use in semiconductor memory'19904,939,695'Virtual type static semiconductor memory device including refresh detector circuitry'19904,905,192'Semiconductor memory cell'19904,894,561'CMOS inverter having temperature and supply voltage variation compensation'19904,855,957'Random access memory including switching elements to limit the number of energized data in pairs'19894,853,897'Complementary semiconductor memory device'19894,769,792'Semiconductor memory device with voltage bootstrap'19884,757,217'Refresh operation control circuit for semiconductor device'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988–2002Patents assigned to TOSHIBA KK (32)· patent assignee history
1988–1991Based in Kawasaki, JP· patent location history
1989–1999Based in Yokohama, JP· patent location history
1990–2004Based in Tokyo, JP· patent location history
1995–1997Based in Palo Alto, CA, US· patent location history
1998–2002Based in Ichikawa, JP· patent location history
2004Patents assigned to THINE ELECTRONICS INC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TOSHIBA KK321988–2002
THINE ELECTRONICS INC12004
Locations
LocationPatentsSpan
Tokyo, JP81990–2004
Yokohama, JP71989–1999
Palo Alto, California, US71995–1997
Kawasaki, JP71988–1991
Ichikawa, JP41998–2002