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Inventor

Anatoli A. Bolotov

Inventor
Cupertino, CA, US

Overview

66→
Patents
2001–2020
Patent span
Physics
Primary field (CPC G)

Patents· 66 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing37%
G11CStatic stores17%
H03MCoding16%
H04LTransmission of digital information, e.g. telegraphic communication11%
G11BInformation storage based on relative movement between record carrier and transducer5%
G01RMeasuring electric variables4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
G06NComputing arrangements based on specific computational models2%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy1%
Y04SSystems integrating technologies related to power network operation, communication or information technologies for improving the electrical power generation, transmission, distribution, management or usage, i.e. smart grids1%
PatentTitleYear
10,846,437Compressed integrity check counters in memory202010,725,861Error correction code memory security20209,553,612'Decoding based on randomized hard decisions'20179,497,160'Symmetric NAT traversal for direct communication in P2P networks when some of the routing NATs are symmetric'20169,417,847'Low depth combinational finite field multiplier'20169,281,843'Systems and methods for reduced constraint code data processing'20169,177,251'Impulse regular expression matching'20159,037,944'Method for selecting a LDPC candidate code'20158,996,971'LDPC decoder trapping set identification'20158,996,969'Low density parity check decoder with miscorrection handling'20158,929,009'Irregular low density parity check decoder with low syndrome error handling'20158,898,539'Correcting errors in miscorrected codewords using list decoding'20148,885,276'Systems and methods for shared layer data decoding'20148,832,532'Dynamically controlling the number of local iterations in an iterative decoder'20148,831,221'Unified architecture for crypto functional units'20148,806,227'Data shredding RAID mode'20148,797,668'Systems and methods for penalty based multi-variant encoding'20148,782,487'Systems and methods for locating and correcting decoder mis-corrections'20148,683,291'High throughput frame check sequence module architecture'20148,654,969'Cipher independent interface for cryptographic hardware service'20148,650,146'Impulse regular expression matching'20148,411,853'Alternate galois field advanced encryption standard round'20138,359,479'High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks'20138,302,083'Architecture and implementation method of programmable arithmetic controller for cryptographic applications'20128,160,242'Efficient implementation of arithmetical secure hash techniques'20128,156,391'Data controlling in the MBIST chain architecture'20128,132,075'Memory mapping for parallel turbo decoding'20128,063,659'Low depth programmable priority encoders'20118,046,643'Transport subsystem for an MBIST chain architecture'20118,023,644'Multimode block cipher architectures'20117,961,872'Flexible hardware architecture for ECC/HECC based cryptography'20117,949,909'Address controlling in the MBIST chain architecture'20117,890,565'Efficient hardware implementation of tweakable block cipher'20117,882,406'Built in test controller with a downloadable testing program'20117,856,577'Command language for memory testing'20107,839,164'Low depth programmable priority encoders'20107,818,703'Density driven layout for RRAM configuration module'20107,788,563'Generation of test sequences during memory built-in self testing of multiple memories'20107,548,844'Sequential tester for longest prefix search engines'20097,430,694'Memory BISR architecture for a slice'20087,415,686'Memory timing model with back-annotating'20087,328,382'Memory BISR controller architecture'20087,308,633'Master controller architecture'20077,305,593'Memory mapping for parallel turbo decoding'20077,283,385'RRAM communication system'20077,246,337'Density driven layout for RRAM configuration module'20077,231,383'Search engine for large-width data'20077,219,321'Process and apparatus for memory mapping'20077,216,278'Method and BIST architecture for fast memory testing in platform-based integrated circuit'20077,200,785'Sequential tester for longest prefix search engines'20077,194,717'Compact custom layout for RRAM column controller'20077,181,563'FIFO memory with single port memory modules for allowing simultaneous read and write operations'20077,082,561'Built-in functional tester for search engines'20067,072,922'Integrated circuit and process for identifying minimum or maximum input value among plural inputs'20067,062,726'Method for generating tech-library for logic function'20067,020,865'Process for designing comparators and adders of small depth'20066,886,088'Memory that allows simultaneous read requests'20056,662,287'Fast free memory address controller'20036,587,990'Method and apparatus for formula area and delay minimization'20036,536,016'Method and apparatus for locating constants in combinational circuits'20036,530,063'Method and apparatus for detecting equivalent and anti-equivalent pins'20036,519,746'Method and apparatus for minimization of net delay by optimal buffer insertion'20036,507,939'Net delay optimization with ramptime violation removal'20036,505,336'Channel router with buffer insertion'20036,453,453'Process for solving assignment problems in integrated circuit designs with unimodal object penalty functions and linearly ordered set of boxes'20026,292,924'Modifying timing graph to avoid given set of paths'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2009Patents assigned to LSI LOGIC CORP (21)· patent assignee history
2002–2014Based in Cupertino, CA, US· patent location history
2003Based in Moscow, RU· patent location history
2007–2016Patents assigned to LSI CORP (39)· patent assignee history
2007Based in Saratoga, CA, US· patent location history
2011–2016Patents assigned to IVANOVIC LAV D (8)· patent assignee history
2012–2016Patents assigned to BOLOTOV ANATOLI A (11)· patent assignee history
2012–2016Patents assigned to GRINCHUK MIKHAIL I (9)· patent assignee history
2014–2020Based in San Jose, CA, US· patent location history
2015Based in Milpitas, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
LSI CORP392007–2016
LSI LOGIC CORP212001–2009
BOLOTOV ANATOLI Aself112012–2016
GRINCHUK MIKHAIL I92012–2016
IVANOVIC LAV D82011–2016
Locations
LocationPatentsSpan
Cupertino, California, US422002–2014
San Jose, California, US172014–2020
Moscow, RU42003
Milpitas, California, US12015
Saratoga, California, US12007