Inventor
Scot A. Kellar
Inventor
Bend, OR, US
Overview
Patents· 14 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
B82YSpecific uses or applications of nanostructures12%
H10DInorganic electric semiconductor devices12%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests12%
G11CStatic stores8%
H01GCapacitors8%
H10BElectronic memory devices8%
Y10TTechnical subjects covered by former us classification8%
H05KPrinted circuits4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
PatentTitleYear
10,068,866Integrated circuit package having rectangular aspect ratio20187,271,434'Capacitor with insulating nanostructure'20077,265,406'Capacitor with conducting nanostructure'20077,244,983'Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode'20077,157,787'Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices'20077,091,084'Ultra-high capacitance device based on nanostructures'20067,056,807'Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack'20067,037,804'Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration'20066,975,016'Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof'20056,911,373'Ultra-high capacitance device based on nanostructures'20056,887,769'Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same'20056,762,076'Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices'20046,661,085'Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack'20036,599,808'Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2018Patents assigned to INTEL CORP (14)· patent assignee history
2003–2018Based in Bend, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 14 | 2003–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bend, OR, US | 14 | 2003–2018 |