Inventor
Daniel E. Grupp
Inventor
Palo Alto, CA, US
Overview
Patents· 40 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices36%
H01LSemiconductor devices16%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
A61BDiagnosis4%
B01LChemical or physical laboratory apparatus for general use3%
G01NInvestigating or analysing materials by determining their chemical or physical properties3%
A01HNew plants or non-transgenic processes for obtaining them2%
B82YSpecific uses or applications of nanostructures2%
C12NMicroorganisms or enzymes2%
PatentTitleYear
11,056,569Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions202111,043,571Insulated gate field effect transistor having passivated schottky barriers to the channel202111,018,237Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions202110,950,707Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions202110,937,880Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions202110,768,166Diagnostics systems and methods202010,388,748Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions201910,375,909Diagnostics systems and methods201910,349,589Diagnostics systems and methods201910,186,592Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions201910,090,395Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions20189,905,691'Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions'20189,812,542'Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions'20179,583,614'Insulated gate field effect transistor having passivated schottky barriers to the channel'20179,461,167'Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions'20169,425,277'Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions'20169,232,959'Multi fluid tissue resection methods and devices'20169,209,261'Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions'20158,916,437'Insulated gate field effect transistor having passivated schottky barriers to the channel'20148,766,336'Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions'20148,658,523'Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)'20148,431,469'Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions'20138,377,767'Insulated gate field effect transistor having passivated schottky barriers to the channel'20138,263,467'Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor'20127,902,029'Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor'20117,884,003'Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions'20117,883,980'Insulated gate field effect transistor having passivated schottky barriers to the channel'20117,816,240'Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)'20107,615,402'Electrostatically operated tunneling transistor'20097,462,860'Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions'20087,382,021'Insulated gate field-effect transistor having III-VI source/drain layer(s)'20087,176,483'Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions'20077,112,478'Insulated gate field effect transistor having passivated Schottky barriers to the channel'20067,084,423'Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions'20066,891,234'Transistor with workfunction-induced charge layer'20056,833,556'Insulated gate field effect transistor having passivated schottky barriers to the channel'20046,261,943'Method for fabricating free-standing thin metal films'20016,236,033'Enhanced optical transmission apparatus utilizing metal films having apertures and periodic surface topography'20016,198,113'Electrostatically operated tunneling transistor'20015,586,064'Active magnetic field compensation system using a single filter'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996Based in Brooklyn, NY, US· patent location history
2001–2021Patents assigned to ACORN TECH INC (29)· patent assignee history
2001–2021Based in Palo Alto, CA, US· patent location history
2001–2009Based in Stockton, NJ, US· patent location history
2012–2016Patents assigned to CONNELLY DANIEL J (5)· patent assignee history
2012–2016Patents assigned to GRUPP DANIEL E (5)· patent assignee history
2014–2021Based in San Francisco, CA, US· patent location history
2019–2020Patents assigned to HEMEX HEALTH INC (3)· patent assignee history
2019–2020Based in Portland, OR, US· patent location history
2021Patents assigned to ACORN SEMI LLC (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ACORN TECH INC | 29 | 2001–2021 |
| ACORN SEMI LLC | 5 | 2021 |
| CONNELLY DANIEL J | 5 | 2012–2016 |
| GRUPP DANIEL Eself | 5 | 2012–2016 |
| HEMEX HEALTH INC | 3 | 2019–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 28 | 2001–2021 |
| San Francisco, California, US | 5 | 2014–2021 |
| Portland, OR, US | 3 | 2019–2020 |
| Stockton, New Jersey, US | 3 | 2001–2009 |
| Brooklyn, New York, US | 1 | 1996 |