Inventor
Vijay Kumar Reddy
Inventor
Plano, TX, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G01Rprimary
G01RMeasuring electric variables35%
H10DInorganic electric semiconductor devices15%
A61KPreparations for medical, dental or toiletry purposes9%
A61PSpecific therapeutic activity of chemical compounds or medicinal preparations9%
C12NMicroorganisms or enzymes9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
G11CStatic stores6%
G06FElectric digital data processing3%
H03FAmplifiers3%
H03KPulse technique3%
PatentTitleYear
10,874,715Methods and compositions for natural killer cells202010,463,715Methods and compositions for natural killer cells20199,778,313'Devices under test'20179,714,966'Circuit aging sensor'20179,623,082'Methods and compositions for natural killer cells'20179,110,111'Methods and systems to determine a final value of random telegraph noise time constant and magnitude'20159,035,706'Variability and aging sensor for integrated circuits'20158,753,941'High performance asymmetric cascoded transistor'20148,239,814'Parameter drift prediction'20128,138,829'Segmented power amplifier with varying segment activation'20127,974,595'Methodology for assessing degradation due to radio frequency excitation of transistors'20117,952,378'Tunable stress technique for reliability degradation measurement'20117,737,717'Current-voltage-based method for evaluating thin dielectrics based on interface traps'20107,385,383'Methods and systems for determining efficacy of stress protection circuitry'20087,263,455'Apparatus and methods for ferroelectric ram fatigue testing'20077,218,132'System and method for accurate negative bias temperature instability characterization'20077,212,023'System and method for accurate negative bias temperature instability characterization'20077,196,887'PMOS electrostatic discharge (ESD) protection device'20077,026,838'Versatile system for accelerated stress characterization of semiconductor device structures'20066,963,111'Efficient pMOS ESD protection circuit'20056,933,731'Method and system for determining transistor degradation mechanisms'20056,928,376'Apparatus and methods for ferroelectric ram fatigue testing'20056,815,970'Method for measuring NBTI degradation effects on integrated circuits'20046,709,932'Method for improving gate oxide integrity and interface quality in a multi-gate oxidation process'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2017Patents assigned to TEXAS INSTRUMENTS INC (21)· patent assignee history
2004–2017Based in Plano, TX, US· patent location history
2012Patents assigned to REDDY VIJAY KUMAR (2)· patent assignee history
2012Patents assigned to GINSBURG BRIAN P (1)· patent assignee history
2012Patents assigned to HUNG CHIH-MING (1)· patent assignee history
2017–2020Patents assigned to UNIV CENTRAL FLORIDA RES FOUND INC (3)· patent assignee history
2017–2020Based in Orlando, FL, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 21 | 2004–2017 |
| UNIV CENTRAL FLORIDA RES FOUND INC | 3 | 2017–2020 |
| REDDY VIJAY KUMARself | 2 | 2012 |
| GINSBURG BRIAN P | 1 | 2012 |
| HUNG CHIH-MING | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Plano, Texas, US | 21 | 2004–2017 |
| Orlando, Florida, US | 3 | 2017–2020 |