Inventor
Dale E. Pontius
Inventor
Colchester, VT, US
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores38%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems15%
G06FElectric digital data processing13%
H03KPulse technique13%
G05FSystems for regulating electric or magnetic variables6%
H05KPrinted circuits6%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%
G01RMeasuring electric variables2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
10,971,996Charge pump circuit with internal pre-charge configuration202110,699,771Voltage boost circuit202010,673,321Charge pump circuit with built-in-retry202010,438,652Voltage boost circuit201910,127,970Voltage boost circuit20189,996,648Netlist editing of graphical data20189,634,557'Voltage boost circuit'20178,300,489'Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pump'20126,882,583'Method and apparatus for implementing DRAM redundancy fuse latches using SRAM'20056,674,676'Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture'20046,674,673'Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture'20046,327,224'On-chip method for measuring access time and data-pin spread'20016,088,206'Clamp circuit to limit overdrive of off chip driver'20006,038,179'Multiple repair size redundancy'20005,963,464'Stackable memory card'19995,920,222'Tunable pulse generator based on a wave pipeline'19995,905,395'Miller effect-based delay circuit'19995,878,094'Noise detection and delay receiver system'19995,809,528'Method and circuit for a least recently used replacement mechanism and invalidated address handling in a fully associative many-way cache memory'19985,745,431'Address transition detector (ATD) for power conservation'19985,614,846'Latch circuit with state-walk logic'19975,606,269'Non-delay based address transition detector (ATD)'19975,555,528'Dynamic random access memory persistent page implemented as processor register sets'19965,545,978'Bandgap reference generator having regulation and kick-start circuits'19965,519,664'Dynamic random access memory persistent page implemented as processor register sets'19965,508,968'Dynamic random access memory persistent page implemented as processor register sets'19965,430,679'Flexible redundancy architecture and fuse download scheme'19955,426,566'Multichip integrated circuit packages and systems'19955,278,800'Memory system and unique memory chip allowing island interlace'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2020Patents assigned to IBM (26)· patent assignee history
1994–2021Based in Colchester, VT, US· patent location history
2012Patents assigned to FIFIELD JOHN A (1)· patent assignee history
2012Patents assigned to MAFFITT THOMAS M (1)· patent assignee history
2018Patents assigned to GLOBALFOUNDRIES INC (1)· patent assignee history
2020–2021Patents assigned to MARVELL ASIA PTE LTD (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 26 | 1994–2020 |
| MARVELL ASIA PTE LTD | 2 | 2020–2021 |
| FIFIELD JOHN A | 1 | 2012 |
| GLOBALFOUNDRIES INC | 1 | 2018 |
| MAFFITT THOMAS M | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Colchester, VT, US | 29 | 1994–2021 |