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Inventor

David E. Lazovsky

Inventor
Los Gatos, CA, US

Overview

39→
Patents
2007–2016
Patent span
Electricity
Primary field (CPC H)

Patents· 39 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
B82YSpecific uses or applications of nanostructures14%
Y10TTechnical subjects covered by former us classification10%
H01LSemiconductor devices7%
C23CCoating metallic material5%
H01JElectric discharge tubes or discharge lamps5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
H10DInorganic electric semiconductor devices5%
H10BElectronic memory devices3%
PatentTitleYear
9,368,400'Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region'20169,362,231'Molecular self-assembly in substrate processing'20169,331,279'Creating an embedded ReRAM memory from a high-k metal gate transistor structure'20169,275,727'Multi-level memory array having resistive elements for multi-bit data storage'20169,275,954'Molecular self-assembly in substrate processing'20169,076,716'Methods for discretized processing and process sequence integration of regions of a substrate'20159,054,032'Creating an embedded ReRAM memory from a high-k metal gate transistor structure'20158,995,166'Multi-level memory array having resistive elements for multi-bit data storage'20158,975,180'Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region'20158,883,633'Molecular self-assembly in substrate processing'20148,882,914'Processing substrates using site-isolated processing'20148,836,123'Methods for discretized formation of masking and capping layers on a substrate'20148,815,753'Molecular self-assembly in substrate processing'20148,803,124'Creating an embedded reram memory from a high-K metal gate transistor structure'20148,776,717'Systems for discretized processing of regions of a substrate'20148,709,943'Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region'20148,697,606'Methods for discretized processing and process sequence integration of regions of a substrate'20148,610,121'Methods for discretized processing and process sequence integration of regions of a substrate'20138,586,485'Molecular self-assembly in substrate processing'20138,575,036'Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region'20138,461,044'Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region'20138,389,445'Methods for discretized processing and process sequence integration of regions of a substrate'20138,372,759'Molecular self-assembly in substrate processing'20138,367,587'Methods for discretized processing and process sequence integration of regions of a substrate'20138,343,866'Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region'20138,193,090'Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region'20128,163,631'Methods for discretized processing and process sequence integration of regions of a substrate'20128,084,400'Methods for discretized processing and process sequence integration of regions of a substrate'20118,067,340'Methods for discretized processing and process sequence integration of regions of a substrate'20118,058,154'Methods for discretized processing and process sequence integration of regions of a substrate'20118,039,383'Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric regions'20118,030,772'Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region'20117,972,972'Molecular self-assembly in substrate processing'20117,902,063'Methods for discretized formation of masking and capping layers on a substrate'20117,871,928'Methods for discretized processing of regions of a substrate'20117,749,881'Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region'20107,544,574'Methods for discretized processing of regions of a substrate'20097,390,739'Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region'20087,309,658'Molecular self-assembly in substrate processing'2007

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2007–2016Patents assigned to INTERMOLECULAR INC (38)· patent assignee history
2007–2014Based in San Jose, CA, US· patent location history
2008–2014Patents assigned to LAZOVSKY DAVID E (17)· patent assignee history
2008–2014Patents assigned to BOUSSIE THOMAS R (13)· patent assignee history
2008–2016Based in Los Gatos, CA, US· patent location history
2011–2014Patents assigned to CHIANG TONY P (14)· patent assignee history
2011–2014Patents assigned to GORER ALEXANDER (9)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTERMOLECULAR INC382007–2016
LAZOVSKY DAVID Eself172008–2014
CHIANG TONY P142011–2014
BOUSSIE THOMAS R132008–2014
GORER ALEXANDER92011–2014
Locations
LocationPatentsSpan
Los Gatos, California, US282008–2016
San Jose, California, US112007–2014