Inventor
Erik E. Hagersten
Inventor
Palo Alto, CA, US
Overview
Patents· 97 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing87%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
PatentTitleYear
11,023,376System and methods for efficient virtually-tagged cache implementation202110,915,466System protecting caches from side-channel attacks202110,884,925Systems and methods for tag-less buffer implementation202110,866,891Systems and methods for efficient compressed cache line storage and handling202010,754,777Systems and methods for implementing coherent memory in a multiprocessor system202010,713,166Efficient early ordering mechanism202010,671,543Systems and methods for reducing first level cache energy by eliminating cache address tags202010,409,725Management of shared pipeline resource usage based on level information201910,402,344Systems and methods for direct data access in multi-level cache memory hierarchies201910,402,331Systems and methods for implementing a tag-less shared cache and a larger backing cache201910,031,849Tracking alternative cacheline placement locations in a cache hierarchy201810,019,368Placement policy for memory hierarchies20188,539,455'System for and method of capturing performance characteristics data from a computer system and modeling target system performance'20138,443,341'System for and method of capturing application characteristics data from a computer system and modeling target system'20138,141,058'System for and method of capturing application characteristics data from a computer system and modeling target system'20128,024,526'Multi-node system with global access states'20118,010,749'Multi-node computer system with proxy transaction to read data from a non-owning memory device'20117,945,738'Multi-node computer system employing a reporting mechanism for multi-node transactions'20117,765,381'Multi-node system in which home memory subsystem stores global to local address translation information for replicating nodes'20107,606,978'Multi-node computer system implementing global access state dependent transactions'20097,529,893'Multi-node system with split ownership and access right coherence mechanism'20097,529,844'Multiprocessing systems employing hierarchical spin locks'20097,509,460'DRAM remote access cache in local memory in a distributed shared memory system'20097,412,567'Value-based memory coherence support'20087,373,461'Speculative directory lookup for sharing classification'20087,363,462'Performing virtual to global address translation in processing subsystem'20087,360,056'Multi-node system in which global address generated by processing subsystem includes global to local translation information'20087,237,068'Computer system employing bundled prefetching and null-data packet transmission'20077,165,146'Multiprocessing computer system employing capacity prefetching'20077,120,756'Computer system including a promise array'20067,080,213'System and method for reducing shared memory write overhead in multiprocessor systems'20066,985,984'Multiprocessing systems employing hierarchical back-off locks'20066,826,660'Hierarchical SMP computer system'20046,772,244'Queuing delay limiter'20046,760,786'Multiprocessing system configured to perform efficient block copy operations'20046,654,866'Skewed finite hashing function'20036,618,799'Selective address translation in coherent memory replication'20036,578,071'Repeater for use in a shared memory computing system'20036,578,033'System and method for accessing a shared computer resource using a lock featuring different spin speeds corresponding to multiple states'20036,574,659'Methods and apparatus for a directory-less memory access protocol in a distributed shared memory computer system'20036,536,000'Communication error reporting mechanism in a multiprocessing computer system'20036,496,854'Hybrid memory access protocol in a distributed shared memory computer system'20026,449,700'Multiprocessing computer system employing a cluster protection mechanism'20026,446,185'Selective address translation in coherent memory replication'20026,401,174'Multiprocessing computer system employing a cluster communication error reporting mechanism'20026,377,980'Methods and apparatus for a directory-less memory access protocol in a distributed shared memory computer system'20026,370,585'Multiprocessing computer system employing a cluster communication launching and addressing mechanism'20026,351,795'Selective address translation in coherent memory replication'20026,332,165'Multiprocessor computer system employing a mechanism for routing communication traffic through a cluster node having a slice of memory directed for pass through transactions'20016,332,169'Multiprocessing system configured to perform efficient block copy operations'20016,308,246'Skewed finite hashing function'20016,243,742'Hybrid memory access protocol in a distributed shared memory computer system'20016,240,501'Cache-less address translation'20016,226,671'Shared memory system for symmetric multiprocessor systems'20016,148,300'Hybrid queue and backoff computer resource lock featuring different spin speeds corresponding to multiple-states'20006,141,692'Directory-based, shared-memory, scaleable multiprocessor computer system having deadlock-free transaction flow sans flow control protocol'20006,078,996'Method for increasing the speed of data processing in a computer system'20005,987,549'Method and apparatus providing short latency round-robin arbitration for access to a shared resource'19995,983,326'Multiprocessing system including an enhanced blocking mechanism for read-to-share-transactions in a NUMA mode'19995,978,874'Implementing snooping on a split-transaction computer system bus'19995,960,179'Method and apparatus extending coherence domain beyond a computer system bus'19995,958,019'Multiprocessing system configured to perform synchronization operations'19995,950,226'Multiprocessing system employing a three-hop communication protocol'19995,940,860'Methods and apparatus for substantially memory-less coherence transformer for connecting computer node coherence domains'19995,926,829'Hybrid NUMA COMA caching system and methods for selecting between the caching modes'19995,923,847'Split-SMP computer system configured to operate in a protected mode having repeater which inhibits transaction to local address partiton'19995,911,052'Split transaction snooping bus protocol'19995,903,907'Skip-level write-through in a multi-level memory of a computer system'19995,897,657'Multiprocessing system employing a coherency protocol including a reply count'19995,892,970'Multiprocessing system configured to perform efficient block copy operations'19995,893,149'Flushing of cache memory in a computer system'19995,893,150'Efficient allocation of cache memory space in a computer system'19995,893,144'Hybrid NUMA COMA caching system and methods for selecting between the caching modes'19995,893,160'Deterministic distributed multi-cache coherence method and system'19995,887,138'Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes'19995,881,303'Multiprocessing system configured to perform prefetch coherency activity with separate reissue queue for each processing subnode'19995,878,268'Multiprocessing system configured to store coherency state within multiple subnodes of a processing node'19995,873,117'Method and apparatus for a directory-less memory access protocol in a distributed shared memory computer system'19995,864,671'Hybrid memory access protocol for servicing memory access request by ascertaining whether the memory block is currently cached in determining which protocols to be used'19995,862,357'Hierarchical SMP computer system'19995,862,316'Multiprocessing system having coherency-related error logging capabilities'19995,860,109'Methods and apparatus for a coherence transformer for connecting computer system coherence domains'19995,860,159'Multiprocessing system including an apparatus for optimizing spin--lock operations'19995,852,716'Split-SMP computer system with local domains and a top repeater that distinguishes local and global transactions'19985,848,254'Multiprocessing system using an access to a second memory space to initiate software controlled data prefetch into a first address space'19985,842,026'Interrupt transfer management process and system for a multi-processor environment'19985,835,906'Methods and apparatus for sharing stored data objects in a computer system'19985,829,033'Optimizing responses in a coherent distributed electronic system including a computer system'19985,829,034'Method and apparatus for a coherence transformer with limited memory for connecting computer system coherence domains'19985,802,563'Efficient storage of data in computer system with multiple cache levels'19985,802,566'Method and system for predicting addresses and prefetching data into a cache memory'19985,796,605'Extended symmetrical multiprocessor address mapping'19985,778,427'Method and apparatus for selecting a way of a multi-way associative cache by storing waylets in a translation structure'19985,754,877'Extended symmetrical multiprocessor architecture'19985,749,095'Multiprocessing system configured to perform efficient write operations'19985,734,922'Multiprocessing system configured to detect and efficiently provide for migratory data access patterns'19985,710,907'Hybrid NUMA COMA caching system and methods for selecting between the caching modes'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2009Patents assigned to SUN MICROSYSTEMS INC (78)· patent assignee history
1998–2008Based in Palo Alto, CA, US· patent location history
1998Based in Mountain View, CA, US· patent location history
2000Based in Mountain View, SE· patent location history
2003–2021Based in Uppsala, SE· patent location history
2010–2011Patents assigned to ORACLE AMERICA INC (4)· patent assignee history
2012–2013Patents assigned to BERG ERIK (3)· patent assignee history
2012–2013Patents assigned to HAGERSTEN ERIK (3)· patent assignee history
2018–2021Patents assigned to SAMSUNG ELECTRONICS CO LTD (12)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SUN MICROSYSTEMS INC | 78 | 1998–2009 |
| SAMSUNG ELECTRONICS CO LTD | 12 | 2018–2021 |
| ORACLE AMERICA INC | 4 | 2010–2011 |
| BERG ERIK | 3 | 2012–2013 |
| HAGERSTEN ERIKself | 3 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 63 | 1998–2008 |
| Uppsala, SE | 32 | 2003–2021 |
| Mountain View, SE | 1 | 2000 |
| Mountain View, California, US | 1 | 1998 |