Inventor
Joseph R. Edwards
Inventor
Rochester, MN, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
10,467,150Dynamic tier remapping of data stored in a hybrid storage system201910,078,595Implementing hardware accelerator for storage write cache management for managing cache destage rates and thresholds for storage write cache201810,067,880Dynamic tier remapping of data stored in a hybrid storage system20189,940,255Implementing hardware accelerator for storage write cache management for identification of data age in storage write cache20189,940,258Implementing hardware accelerator for storage write cache management for merging data with existing data on fast writes to storage write cache20189,940,257Implementing hardware accelerator for storage write cache management for managing cache line updates for purges from storage write cache20189,940,251Implementing hardware accelerator for storage write cache management for reads from storage write cache20189,940,249Implementing hardware accelerator for storage write cache management with cache line manipulation20189,940,250Implementing hardware accelerator for storage write cache management for writes to storage write cache20189,940,256Implementing hardware accelerator for storage write cache management for managing cache line updates for writes, reads, and destages in storage write cache20189,940,254Implementing hardware accelerator for storage write cache management for simultaneous read and destage operations from storage write cache20189,940,253Implementing hardware accelerator for storage write cache management for destage operations from storage write cache20189,940,252Implementing hardware accelerator for storage write cache management for reads with partial read hits from storage write cache20189,864,695'Implementing hardware accelerator for storage write cache management for managing cache destage rates and thresholds for storage write cache'20189,658,968'Implementing hardware accelerator for storage write cache management'20179,009,490'Implementing dynamic banding of self encrypting drive'20157,979,655'Dynamic optimization of device limits and thresholds in a write cache'20117,925,837'Maintaining write cache and parity update footprint coherency in multiple storage adaptor configuration'20117,243,343'Method, compiler and platform independent framework for parsing and generating data structures'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2019Patents assigned to IBM (19)· patent assignee history
2007–2019Based in Rochester, MN, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 19 | 2007–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Rochester, Minnesota, US | 19 | 2007–2019 |