Inventor
William N. Thompson
Inventor
Meridian, ID, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores52%
H03HImpedance networks, e.g. resonant circuits22%
H10BElectronic memory devices13%
G06FElectric digital data processing7%
H03KPulse technique7%
PatentTitleYear
7,190,610'Latch-up prevention for memory cells'20077,180,386'Variable resistance circuit'20077,018,889'Latch-up prevention for memory cells'20066,958,661'Variable resistance circuit'20056,865,628'Output data path capable of multiple data rates'20056,823,407'Output data path capable of multiple data rates'20046,767,784'Latch-up prevention for memory cells'20046,657,512'Method to find a value within a range using weighted subranges'20036,642,588'Latch-up prevention for memory cells'20036,556,095'Method to find a value within a range using weighted subranges'20036,545,561'Method to find a value within a range using weighted subranges'20036,545,560'Method to find a value within a range using weighted subranges'20036,516,363'Output data path having selectable data rates'20036,476,640'Method for buffering an input signal'20026,469,591'Method to find a value within a range using weighted subranges'20026,445,259'Method to find a value within a range using weighted subranges'20026,384,714'Method to find a value within a range using weighted subranges'20026,376,297'Latch-up prevention for memory cells'20026,310,820'Relaxed write timing for a memory device'20016,301,188'Method and apparatus for registering free flow information'20016,275,119'Method to find a value within a range using weighted subranges'20016,239,618'Buffer with fast edge propagation'20016,128,244'Method and apparatus for accessing one of a plurality of memory units within an electronic memory device'20006,088,278'Latching sense amplifier structure with pre-amplifier'20006,040,713'Buffer with fast edge propagation'20006,026,031'Relaxed write timing for a memory device'20006,005,797'Latch-up prevention for memory cells'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2007Patents assigned to MICRON TECHNOLOGY INC (27)· patent assignee history
1999–2007Based in Meridian, ID, US· patent location history
2006Based in Meridan, ID, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 27 | 1999–2007 |
Locations
| Location | Patents | Span |
|---|---|---|
| Meridian, ID, US | 26 | 1999–2007 |
| Meridan, ID, US | 1 | 2006 |