Inventor
David W. Daniel
Inventor
Divide, CO, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1028%
H10DInorganic electric semiconductor devices18%
B24BMachines, devices, or processes for grinding or polishing13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
B82YSpecific uses or applications of nanostructures3%
E02BHydraulic engineering3%
G01NInvestigating or analysing materials by determining their chemical or physical properties3%
G06FElectric digital data processing3%
H04LTransmission of digital information, e.g. telegraphic communication3%
PatentTitleYear
11,095,675System and method for identifying system vulnerabilities20217,095,483'Process independent alignment marks'20066,870,160'Method and apparatus for monitoring the condition of a lubricating medium'20056,856,029'Process independent alignment marks'20056,506,684'Anti-corrosion system'20036,372,520'Sonic assisted strengthening of gate oxides'20026,354,908'Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system'20026,355,532'Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET'20026,316,817'MeV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor'20016,241,847'Method and apparatus for detecting a polishing endpoint based upon infrared signals'20016,235,590'Fabrication of differential gate oxide thicknesses on a single integrated circuit chip'20016,201,253'Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system'20016,121,147'Apparatus and method of detecting a polishing endpoint layer of a semiconductor wafer which includes a metallic reporting substance'20006,096,625'Method for improved gate oxide integrity on bulk silicon'20006,077,783'Method and apparatus for detecting a polishing endpoint based upon heat conducted through a semiconductor wafer'20006,069,048'Reduction of silicon defect induced failures as a result of implants in CMOS and other integrated circuits'20005,966,599'Method for fabricating a low trigger voltage silicon controlled rectifier and thick field device'19995,858,828'Use of MEV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor'19994,150,909'Breakwater system'1979Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1979Patents assigned to DANIEL DAVID W (1)· patent assignee history
1979Patents assigned to HIBARGER GEORGE E (1)· patent assignee history
1979Patents assigned to HIBARGER GEORGE G (1)· patent assignee history
1979Based in Tulsa, OK, US· patent location history
1999–2006Patents assigned to LSI LOGIC CORP (16)· patent assignee history
1999–2002Based in Divide, CO, US· patent location history
2002–2006Based in Vancouver, WA, US· patent location history
2021Patents assigned to NATIONWIDE MUTUAL INSURANCE COMPANY (1)· patent assignee history
2021Based in Hillard, OH, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 16 | 1999–2006 |
| DANIEL DAVID Wself | 1 | 1979 |
| HIBARGER GEORGE E | 1 | 1979 |
| HIBARGER GEORGE G | 1 | 1979 |
| NATIONWIDE MUTUAL INSURANCE COMPANY | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Divide, CO, US | 12 | 1999–2002 |
| Vancouver, Washington, US | 5 | 2002–2006 |
| Hillard, OH, US | 1 | 2021 |
| Tulsa, OK, US | 1 | 1979 |