LexDanaLexDanabeta
Inventor

Frank Scott Johnson

Inventor
Richardson, TX, US

Overview

62→
Patents
1978–2016
Patent span
Electricity
Primary field (CPC H)

Patents· 62 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices56%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
H01LSemiconductor devices6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
A47BTables2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
G06FElectric digital data processing1%
G09FDisplaying1%
H01FMagnets1%
PatentTitleYear
9,336,345'Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits'20169,257,325'Semiconductor structures and methods for forming isolation between Fin structures of FinFET devices'20169,123,570'Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates'20159,000,534'Method for forming and integrating metal gate transistors having self-aligned contacts and related structure'20158,912,603'Semiconductor device with stressed fin sections'20148,865,596'Methods for forming semiconductor structures using selectively-formed sidewall spacers'20148,736,061'Integrated circuits having a continuous active area and methods for fabricating same'20148,729,609'Integrated circuits including multi-gate transistors locally interconnected by continuous fin structure and methods for the fabrication thereof'20148,603,893'Methods for fabricating FinFET integrated circuits on bulk semiconductor substrates'20138,558,318'Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates'20138,404,592'Methods for fabricating FinFET semiconductor devices using L-shaped spacers'20138,383,503'Methods for forming semiconductor structures using selectively-formed sidewall spacers'20138,268,727'Methods for fabricating FinFET semiconductor devices using planarized spacers'20128,192,641'Methods for fabricating non-planar electronic devices having sidewall spacers formed adjacent selected surfaces'20128,138,045'Method of forming sidewall spacers to reduce formation of recesses in the substrate and increase dopant retention in a semiconductor device'20128,039,349'Methods for fabricating non-planar semiconductor devices having stress memory'20118,039,326'Methods for fabricating bulk FinFET devices having deep trench isolation'20118,030,144'Semiconductor device with stressed fin sections, and related fabrication methods'20117,985,639'Method for fabricating a semiconductor device having a semiconductive resistor structure'20117,977,174'FinFET structures with stress-inducing source/drain-forming spacers and methods for fabricating the same'20117,960,287'Methods for fabricating FinFET structures having different channel lengths'20117,960,280'Process method to fully salicide (FUSI) both N-poly and P-poly on a CMOS flow'20117,943,451'Integration scheme for reducing border region morphology in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates'20117,930,656'System and method for making photomasks'20117,910,422'Reducing gate CD bias in CMOS processing'20117,892,908'Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates'20117,892,906'Method for forming CMOS transistors having FUSI gate electrodes and targeted work functions'20117,829,466'Methods for fabricating FinFET structures having different channel lengths'20107,785,970'Method of forming source and drain regions utilizing dual capping layers and split thermal processes'20107,763,540'Method of forming a silicided gate utilizing a CMP stack'20107,687,339'Methods for fabricating FinFET structures having different channel lengths'20107,572,693'Methods for transistor formation using selective gate implantation'20097,456,070'Method of fabricating a bipolar transistor with high breakdown voltage collector'20087,098,098'Methods for transistors formation using selective gate implantation'20066,969,880'High capacitive density stacked decoupling capacitor structure'20056,797,577'One mask PNP (or NPN) transistor allowing high performance'20046,682,994'Methods for transistor gate formation using gate sidewall implantation'20046,645,804'System for fabricating a metal/anti-reflective coating/insulator/metal (MAIM) capacitor'20036,620,700'Silicided undoped polysilicon for capacitor bottom plate'20036,570,242'Bipolar transistor with high breakdown voltage collector'20036,518,111'Method for manufacturing and structure of semiconductor device with dielectric diffusion source and CMOS integration'20036,501,152'Advanced lateral PNP by implant negation'20026,441,715'Method of fabricating a miniaturized integrated circuit inductor and transformer fabrication'20026,380,609'Silicided undoped polysilicon for capacitor bottom plate'20026,281,530'LPNP utilizing base ballast resistor'20016,248,650'Self-aligned BJT emitter contact'20016,239,477'Self-aligned transistor contact for epitaxial layers'20016,194,280'Method for forming a self-aligned BJT emitter contact'20016,130,136'Bipolar transistor with L-shaped base-emitter spacer'20006,130,122'Method for forming a BiCMOS integrated circuit with Nwell compensation implant and method'20006,030,864'Vertical NPN transistor for 0.35 micrometer node CMOS logic technology'20006,030,874'Doped polysilicon to retard boron diffusion into and through thin gate dielectrics'20006,028,345'Reduced resistance base contact for single polysilicon bipolar transistors using extrinsic base diffusion from a diffusion source dielectric layer'20005,629,556'High speed bipolar transistor using a patterned etch stop and diffusion source'19975,616,508'High speed bipolar transistor using a patterned etch stop and diffusion source'19975,593,905'Method of forming stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link'19975,592,017'Self-aligned double poly BJT using sige spacers as extrinsic base contacts'19975,541,121'Reduced resistance base contact method for single polysilicon bipolar transistors using extrinsic base diffusion from a diffusion source dielectric layer'19965,502,330'Stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link'19964,208,098'Odor dispensing system for hand-held stereoscopic viewer and replaceable container therefor'19804,201,428'Cabinet assembly'19804,090,755'Cabinet assembly'1978

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1980–2014Patents assigned to JOHNSON FRANK (2)· patent assignee history
1996–2015Patents assigned to TEXAS INSTRUMENTS INC (39)· patent assignee history
1996–2000Based in Plano, TX, US· patent location history
2000–2011Based in Richardson, TX, US· patent location history
2001–2002Based in Garland, TX, US· patent location history
2010–2016Patents assigned to GLOBALFOUNDRIES INC (18)· patent assignee history
2010–2016Based in Wappingers Falls, NY, US· patent location history
2011–2014Based in Wappinger Falls, NY, US· patent location history
2012–2016Patents assigned to JOHNSON FRANK SCOTT (9)· patent assignee history
2012–2013Patents assigned to JOHNSON FRANK S (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TEXAS INSTRUMENTS INC391996–2015
GLOBALFOUNDRIES INC182010–2016
JOHNSON FRANK SCOTTself92012–2016
JOHNSON FRANK Sself32012–2013
JOHNSON FRANKself21980–2014
Locations
LocationPatentsSpan
Richardson, Texas, US212000–2011
Wappingers Falls, New York, US182010–2016
Wappinger Falls, New York, US72011–2014
Plano, Texas, US71996–2000
Garland, Texas, US42001–2002