LexDanaLexDanabeta
Inventor

Mahmud Assar

Inventor
Morgan Hill, CA, US

Overview

40→
Patents
1990–2014
Patent span
Physics
Primary field (CPC G)

Patents· 40 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores36%
G06FElectric digital data processing29%
H10BElectronic memory devices11%
B82YSpecific uses or applications of nanostructures7%
H10NElectric solid-state devices not otherwise provided for7%
H03KPulse technique5%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
G01RMeasuring electric variables1%
G06KGraphical data reading1%
H10DInorganic electric semiconductor devices1%
PatentTitleYear
8,724,413'High capacity low cost multi-state magnetic memory'20148,711,613'Non-volatile flash-RAM memory with magnetic memory'20148,477,530'Non-uniform switching based non-volatile magnetic based memory'20138,440,471'Low-cost non-volatile flash-RAM memory'20138,391,054'High-capacity low cost multi-state magnetic memory'20138,389,301'Non-uniform switching based non-volatile magnetic based memory'20138,391,058'Low-cost non-volatile flash-RAM memory'20138,291,128'Systems configured to identify an operating mode'20128,120,949'Low-cost non-volatile flash-RAM memory'20128,084,835'Non-uniform switching based non-volatile magnetic based memory'20118,073,986'Memory devices configured to identify an operating mode'20118,058,696'High capacity low cost multi-state magnetic memory'20118,032,694'Direct logical block addressing flash memory mass storage architecture'20117,774,576'Direct logical block addressing flash memory mass storage architecture'20107,721,017'Methods and apparatus for identifying operating modes for peripheral devices'20107,523,249'Direct logical block addressing flash memory mass storage architecture'20097,421,523'Flash memory card with enhanced operating mode detection and user-friendly interfacing system'20087,174,445'Flash memory card with enhanced operating mode detection and user-friendly interfacing system'20077,111,085'Flash memory card with enhanced operating mode detection and user-friendly interfacing system'20066,912,618'Direct logical block addressing flash memory mass storage architecture'20056,721,819'Flash memory card with enhanced operating mode detection and user-friendly interfacing system'20046,587,382'Nonvolatile memory using flexible erasing methods and method and system for using same'20036,411,546'Nonvolatile memory using flexible erasing methods and method and system for using same'20026,404,246'Precision clock synthesizer using RC oscillator and calibration circuit'20026,385,667'System for configuring a flash memory card with enhanced operating mode detection and user-friendly interfacing system'20026,182,162'Externally coupled compact flash memory card that configures itself one of a plurality of appropriate operating protocol modes of a host computer'20015,926,055'Five volt output connection for a chip manufactured in a three volt process'19995,924,113'Direct logical block addressing flash memory mass storage architecture'19995,845,313'Direct logical block addressing flash memory mass storage architecture'19985,835,935'Method of and architecture for controlling system data with automatic wear leveling in a semiconductor non-volatile mass storage memory'19985,818,781'Automatic voltage detection in multiple voltage applications'19985,818,350'High performance method of and system for selecting one of a plurality of IC chip while requiring minimal select lines'19985,596,526'Non-volatile memory system of multi-level transistor cells and methods using same'19975,523,724'Fast recovering charge pump for controlling a VCO in a low power clocking circuit'19965,485,595'Flash memory mass storage architecture incorporating wear leveling technique without using cam cells'19965,479,638'Flash memory mass storage architecture incorporation wear leveling technique'19955,388,083'Flash memory mass storage architecture'19955,300,835'CMOS low power mixed voltage bidirectional I/O buffer'19945,157,618'Programmable tiles'19924,931,946'Programmable tiles'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2012Based in Morgan Hill, CA, US· patent location history
1998–2010Patents assigned to LEXAR MEDIA INC (14)· patent assignee history
2011–2014Patents assigned to ASSAR MAHMUD (11)· patent assignee history
2011–2014Patents assigned to AVALANCHE TECHNOLOGY INC (10)· patent assignee history
2011–2014Patents assigned to KESHTBOD PARVIZ (9)· patent assignee history
2011–2014Patents assigned to RANJAN RAJIV YADAV (9)· patent assignee history
2011–2014Based in Aptos, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
LEXAR MEDIA INC141998–2010
ASSAR MAHMUDself112011–2014
AVALANCHE TECHNOLOGY INC102011–2014
KESHTBOD PARVIZ92011–2014
RANJAN RAJIV YADAV92011–2014
Locations
LocationPatentsSpan
Morgan Hill, California, US301990–2012
Aptos, California, US102011–2014