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Inventor

Michael C. Parris

Inventor
Colorado Springs, CO, US

Overview

64→
Patents
1989–2017
Patent span
Physics
Primary field (CPC G)

Patents· 64 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores57%
H03KPulse technique10%
G06FElectric digital data processing9%
G01RMeasuring electric variables6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
H10DInorganic electric semiconductor devices5%
H01LSemiconductor devices3%
H10BElectronic memory devices2%
G05FSystems for regulating electric or magnetic variables1%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%
PatentTitleYear
9,558,808'DRAM security erase'20179,557,364'System and method for testing fuse blow reliability for integrated circuits'20179,299,417'DRAM security erase'20169,230,814'Non-volatile memory devices having vertical drain to gate capacitive coupling'20169,158,352'Power boosting circuit for semiconductor packaging'20158,976,572'DRAM security erase'20158,970,003'Embedded passive integration'20158,873,302'Common doped region with separate gate control for a logic compatible non-volatile memory cell'20148,736,278'System and method for testing fuse blow reliability for integrated circuits'20148,699,263'DRAM security erase'20148,692,611'Power boosting circuit for semiconductor packaging'2014RE044726'Data inversion register technique for integrated circuit memory testing'20148,339,882'Dual bit line precharge architecture and method for low power dynamic random access memory (DRAM) integrated circuit devices and devices incorporating embedded DRAM'20128,281,219'Error correction code (ECC) circuit test mode'20127,916,567'Twin cell architecture for integrated circuit dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM'20117,649,406'Short-circuit charge-sharing technique for integrated circuit devices'20107,631,233'Data inversion register technique for integrated circuit memory testing'20097,609,570'Switched capacitor charge sharing technique for integrated circuit devices enabling signal generation of disparate selected signal values'20097,606,093'Optimized charge sharing for data bus skew applications'20097,586,355'Low skew clock distribution tree'20097,580,304'Multiple bus charge sharing'20097,506,100'Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks'20097,463,054'Data bus charge-sharing technique for integrated circuit devices'20087,298,171'Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices'20077,180,363'Powergating method and apparatus'20077,161,214'Reduced gate delay multiplexed interface and output buffer circuit for integrated circuit devices incorporating random access memory arrays'20077,154,795'Clock signal initiated precharge technique for active memory subarrays in dynamic random access memory (DRAM) devices and other integrated circuit devices incorporating embedded DRAM'20067,110,306'Dual access DRAM'20067,099,234'Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM'20067,053,692'Powergate control using boosted and negative voltages'20067,002,874'Dual word line mode for DRAMs'20066,912,168'Non-contiguous masked refresh for an integrated circuit memory'20056,788,590'Bitline reference voltage circuit'20046,744,690'Asynchronous input data path technique for increasing speed and reducing latency in integrated circuit devices incorporating dynamic random access memory (DRAM) arrays and embedded DRAM'20046,738,302'Optimized read data amplifier and method for operating the same in conjunction with integrated circuit devices incorporating memory arrays'20046,731,156'High voltage transistor protection technique and switching circuit for integrated circuit devices utilizing multiple power supply voltages'20046,732,305'Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry'20046,728,931'Time data compression technique for high speed integrated circuit memory devices'20046,657,461'System and method for high speed integrated circuit device testing utilizing a lower speed test environment'20036,643,212'Simultaneous function dynamic random access memory device technique'20036,625,069'Data path decoding technique for an embedded memory array'20036,625,066'Data path decoding technique for an embedded memory array'20036,608,797'Automatic delay technique for early read and write operations in synchronous dynamic random access memories'20036,597,201'Dynamic predecoder circuitry for memory circuits'20036,570,799'Precharge and reference voltage technique for dynamic random access memories'20036,549,470'Small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays'20036,515,926'Shared sense amplifier driver technique for dynamic random access memories exhibiting improved write recovery time'20036,512,394'Technique for efficient logic power gating with data retention in integrated circuit devices'20036,501,817'Area efficient redundancy multiplexer circuit technique for integrated circuit devices providing significantly reduced parasitic capacitance'20026,414,897'Local write driver circuit for an integrated circuit device incorporating embedded dynamic random access memory (DRAM)'20026,317,007'Delayed start oscillator circuit'20016,262,935'Shift redundancy scheme for wordlines in memory circuits'20016,160,743'Self-timed data amplifier and method for an integrated circuit memory device'20005,763,298'Bond pad option for integrated circuits'19985,698,903'Bond pad option for integrated circuits'19975,680,362'Circuit and method for accessing memory cells of a memory device'19975,671,392'Memory device circuit and method for concurrently addressing columns of multiple banks of multi-bank memory array'19975,430,680'DRAM having self-timed burst refresh mode'19955,331,601'DRAM variable row select'19944,918,654'SRAM with programmable capacitance divider'19904,914,627'One transistor memory cell with programmable capacitance divider'19904,910,708'Dram with programmable capacitance divider'19904,893,272'Ferroelectric retention method'19904,853,893'Data storage device and method of using a ferroelectric capacitance divider'1989

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1989–2017Based in Colorado Springs, CO, US· patent location history
1994–2010Patents assigned to UNITED MEMORIES INC (31)· patent assignee history
1994–1998Patents assigned to NIPPON STEEL SEMICONDUCTOR (6)· patent assignee history
2001–2010Patents assigned to SONY CORP (33)· patent assignee history
2012–2014Patents assigned to PARRIS MICHAEL C (5)· patent assignee history
2014–2017Patents assigned to TESSERA INC (9)· patent assignee history
2014–2017Based in San Jose, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SONY CORP332001–2010
UNITED MEMORIES INC311994–2010
TESSERA INC92014–2017
NIPPON STEEL SEMICONDUCTOR61994–1998
PARRIS MICHAEL Cself52012–2014
Locations
LocationPatentsSpan
Colorado Springs, CO, US591989–2017
San Jose, California, US52014–2017