Inventor

Bruce Leroy Beukema

Inventor

Hayfield, MN, US

Overview

1992–2015

Patent span

Physics

Primary field (CPC G)

Patents· 46 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing59%

H04LTransmission of digital information, e.g. telegraphic communication39%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

PatentTitleYear

8,935,333'Implementing multicast on a system area network channel adapter'2015 8,069,353'Low-latency data decryption interface'2011 7,979,548'Hardware enforcement of logical partitioning of a channel adapter\'s resources in a system area network'2011 7,970,952'Performance counters for virtualized network interfaces of communications networks'2011 7,948,894'Data flow control for simultaneous packet reception'2011 7,895,383'Event queue in a logical partition'2011 7,873,751'Infiniband multicast operation in an LPAR environment'2011 7,840,757'Method and apparatus for providing high speed memory for a processing unit'2010 7,660,247'Dynamic load-based credit distribution'2010 7,577,794'Low latency coherency protocol for a multi-chip multiprocessor system'2009 7,555,002'Infiniband general services queue pair virtualization for multiple logical ports on a single physical port'2009 7,548,964'Performance counters for virtualized network interfaces of communications networks'2009 7,500,062'Fast path memory read request processing in a multi-level memory architecture'2009 7,496,753'Data encryption interface for reducing encrypt latency impact on standard traffic'2009 7,428,598'Infiniband multicast operation in an LPAR environment'2008 7,409,558'Low-latency data decryption interface'2008 7,385,925'Data flow control method for simultaneous packet reception'2008 7,366,813'Event queue in a logical partition'2008 7,362,705'Dynamic load-based credit distribution'2008 7,296,108'Apparatus and method for efficient transmission of unaligned data'2007 7,290,077'Event queue structure and method'2007 7,283,473'Apparatus, system and method for providing multiple logical channel adapters within a single physical channel adapter in a system area network'2007 7,197,536'Primitive communication mechanism for adjacent nodes in a clustered computer system'2007 7,188,198'Method for implementing dynamic virtual lane buffer reconfiguration'2007 7,149,220'System, method, and product for managing data transfers in a network'2006 7,113,995'Method and apparatus for reporting unauthorized attempts to access nodes in a network computing system'2006 7,010,633'Apparatus, system and method for controlling access to facilities based on usage classes'2006 6,978,300'Method and apparatus to perform fabric management'2005 6,938,138'Method and apparatus for managing access to memory'2005 6,920,519'System and method for supporting access to multiple I/O hub nodes in a host bridge'2005 6,785,759'System and method for sharing I/O address translation caching across multiple host bridges'2004 6,754,753'Atomic ownership change operation for input/output (I/O) bridge device in clustered computer system'2004 6,748,499'Sharing memory tables between host channel adapters'2004 6,691,217'Method and apparatus for associating memory windows with memory regions in a data storage system'2004 6,601,148'Infiniband memory windows management directly in hardware'2003 6,578,122'Using an access key to protect and point to regions in windows for infiniband'2003 6,529,991'Ordering mechanism, ordering method and computer program product for implementing PCI peer to functions'2003 6,275,876'Specifying wrap register for storing memory address to store completion status of instruction to external device'2001 6,185,642'Bus for high frequency operation with backward compatibility and hot-plug ability'2001 6,128,674'Method of minimizing host CPU utilization in driving an adapter by residing in system memory a command/status block a soft interrupt block and a status block queue'2000 5,781,763'Independent control of DMA and I/O resources for mixed-endian computing systems'1998 5,586,265'Priority arbitrating interface for a plurality of shared subsystems coupled to a plurality of system processing devices for selective association of subsystem to processing device'1996 5,584,033'Apparatus and method for burst data transfer employing a pause at fixed data intervals'1996 5,506,964'System with multiple interface logic circuits including arbitration logic for individually linking multiple processing systems to at least one remote sub-system'1996 5,146,605'Direct control facility for multiprocessor network'1992 5,081,624'Fault-tolerant serial attachment of remote high-speed I/O busses'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–2015Patents assigned to IBM (46)· patent assignee history

1992–2015Based in Hayfield, MN, US· patent location history

2011Patents assigned to BEUKEMA BRUCE L (1)· patent assignee history

2011Patents assigned to DREHMEL ROBERT A (1)· patent assignee history

2011Patents assigned to HALL WILLIAM E (1)· patent assignee history

2015Patents assigned to BEUKEMA BRUCE LEROY (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	46	1992–2015
BEUKEMA BRUCE Lself	1	2011
BEUKEMA BRUCE LEROYself	1	2015
DREHMEL ROBERT A	1	2011
HALL WILLIAM E	1	2011

Locations

Location	Patents	Span
Hayfield, Minnesota, US	46	1992–2015