Inventor

Elyar E. Gasanov

Inventor

Moscow, RU

Overview

2001–2021

Patent span

Physics

Primary field (CPC G)

Patents· 62 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing49%

H03MCoding35%

H04LTransmission of digital information, e.g. telegraphic communication14%

G11BInformation storage based on relative movement between record carrier and transducer1%

H04BTransmission1%

PatentTitleYear

11,095,317Efficiently decodable QC-LDPC code2021 10,879,927Compact low density parity check (LDPC) base graph2020 10,862,626Multi-label offset lifting method2020 10,735,138Multi-label offset lifting method2020 10,594,339Method for generating parity check matrix for low density parity check coding2020 10,567,002Method and apparatus for encoding and decoding LDPC codes2020 9,553,612'Decoding based on randomized hard decisions'2017 9,337,866'Apparatus for processing signals carrying modulation-encoded parity bits'2016 9,331,716'Systems and methods for area efficient data encoding'2016 9,319,181'Parallel decoder for multiple wireless standards'2016 8,938,654'Programmable circuit for high speed computation of the interleaver tables for multiple wireless standards'2015 8,923,315'Packet router having a hierarchical buffer structure'2014 8,923,413'Optimization of data processors with irregular patterns'2014 8,868,890'No-delay microsequencer'2014 8,850,437'Two-pass linear complexity task scheduler'2014 8,842,784'L-value generation in a decoder'2014 8,775,893'Variable parity encoder'2014 8,775,914'Radix-4 viterbi forward error correction decoding'2014 8,699,396'Branch metrics calculation for multiple communications standards'2014 8,700,969'Reconfigurable encoding per multiple communications standards'2014 8,656,206'Timer manager architecture based on binary heap'2014 8,621,329'Reconfigurable BCH decoder'2013 8,539,009'Parallel true random number generator architecture'2013 8,527,851'System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors'2013 8,397,143'BCH or reed-solomon decoder with syndrome modification'2013 8,365,054'Soft reed-solomon decoder based on error-and-erasure reed-solomon decoder'2013 8,286,060'Scheme for erasure locator polynomial calculation in error-and-erasure decoder'2012 8,209,589'Reed-solomon decoder with a variable number of correctable errors'2012 8,181,096'Configurable Reed-Solomon decoder based on modified Forney syndromes'2012 8,176,397'Variable redundancy reed-solomon encoder'2012 7,823,050'Low area architecture in BCH decoder'2010 7,568,175'Ramptime propagation on designs with cycles'2009 7,496,870'Method of selecting cells in logic restructuring'2009 7,401,313'Method and apparatus for controlling congestion during integrated circuit design resynthesis'2008 7,398,486'Method and apparatus for performing logical transformations for global routing'2008 7,257,791'Multiple buffer insertion in global routing'2007 7,246,336'Ramptime propagation on designs with cycles'2007 7,146,591'Method of selecting cells in logic restructuring'2006 7,111,267'Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths'2006 7,103,865'Process and apparatus for placement of megacells in ICs design'2006 7,003,739'Method and apparatus for finding optimal unification substitution for formulas in technology library'2006 6,868,536'Method to find boolean function symmetries'2005 6,845,495'Multidirectional router'2005 6,810,515'Process of restructuring logics in ICs for setup and hold time optimization'2004 6,701,493'Floor plan tester for integrated circuit design'2004 6,701,503'Overlap remover manager'2004 6,681,373'Method and apparatus for dynamic buffer and inverter tree optimization'2004 6,637,016'Assignment of cell coordinates'2003 6,637,011'Method and apparatus for quick search for identities applicable to specified formula'2003 6,629,304'Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells'2003 6,615,401'Blocked net buffer insertion'2003 6,564,361'Method and apparatus for timing driven resynthesis'2003 6,553,551'Timing recomputation'2003 6,550,044'Method in integrating clock tree synthesis and timing optimization for an integrated circuit design'2003 6,550,045'Changing clock delays in an integrated circuit for skew optimization'2003 6,543,032'Method and apparatus for local resynthesis of logic trees with multiple cost functions'2003 6,532,582'Method and apparatus for optimal critical netlist area selection'2003 6,513,148'Density driven assignment of coordinates'2003 6,470,487'Parallelization of resynthesis'2002 6,324,674'Method and apparatus for parallel simultaneous global and detail routing'2001 6,253,363'Net routing using basis element decomposition'2001 6,175,950'Method and apparatus for hierarchical global routing descend'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2006Patents assigned to LSI LOGIC CORP (25)· patent assignee history

2001–2021Based in Moscow, RU· patent location history

2007–2016Patents assigned to LSI CORP (24)· patent assignee history

2012–2016Patents assigned to GASANOV ELYAR E (17)· patent assignee history

2012–2016Patents assigned to NEZNANOV ILYA V (16)· patent assignee history

2012–2016Patents assigned to PANTELEEV PAVEL A (16)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
LSI LOGIC CORP	25	2001–2006
LSI CORP	24	2007–2016
GASANOV ELYAR Eself	17	2012–2016
NEZNANOV ILYA V	16	2012–2016
PANTELEEV PAVEL A	16	2012–2016

Locations

Location	Patents	Span
Moscow, RU	62	2001–2021