Inventor
Naoki Kasai
Inventor
Tokyo, JP
Overview
Patents· 31 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices31%
H10DInorganic electric semiconductor devices22%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
G11CStatic stores4%
B82YSpecific uses or applications of nanostructures3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
G01RMeasuring electric variables1%
H01JElectric discharge tubes or discharge lamps1%
H10NElectric solid-state devices not otherwise provided for1%
PatentTitleYear
7,848,137'MRAM and data read/write method for MRAM'20106,768,151'Semiconductor memory device with memory cells having same characteristics and manufacturing method for the same'20046,653,690'Semiconductor device comprising high density integrated circuit having a large number of insulated gate field effect transistors'20036,465,826'Embedded LSI having a FeRAM section and a logic circuit section'20026,448,597'DRAM having a stacked capacitor and a method for fabricating the same'20026,352,891'Method of manufacturing semiconductor device in which hot carrier resistance can be improved and silicide layer can be formed with high reliability'20026,348,408'Semiconductor device with reduced number of intermediate level interconnection pattern and method of forming the same'20026,300,647'Characteristic-evaluating storage capacitors'20016,255,218'Semiconductor device and fabrication method thereof'20016,235,575'Semiconductor device and method for manufacturing same'20016,218,197'Embedded LSI having a FeRAM section and a logic circuit section'20016,190,987'MOS semiconductor device and method of manufacturing the same'20016,034,384'Semiconductor memory device having memory cells similarly layouted and peripheral circuits symmetrically layouted in memory cell arrays'20006,030,894'Method for manufacturing a semiconductor device having contact plug made of Si/SiGe/Si'20005,973,371'Semiconductor device with marginless contact hole'19995,968,692'Integrated circuit pattern lithography method capable of reducing the number of shots in partial batch exposure'19995,946,570'Process for fabricating semiconductor device having semiconductor layers epitaxially grown from active areas without short-circuit on field insulating layer'19995,912,509'MOS semiconductor device and method of manufacturing the same'19995,913,121'Method of making a self-aligning type contact hole for a semiconductor device'19995,909,059'Semiconductor device having contact plug and method for manufacturing the same'19995,907,788'Semiconductor device capable of easily filling contact conductor plug in contact hole'19995,905,283'Method of forming a MOS transistor having gate insulators of different thicknesses'19995,895,948'Semiconductor device and fabrication process thereof'19995,856,938'Small-sized multi-valued semiconductor memory device with coupled capacitors between divided bit lines'19995,840,621'Method for manufacturing contact structure capable of avoiding short-circuit'19985,821,594'Semiconductor device having a self-aligned type contact hole'19985,811,336'Method of forming MOS transistors having gate insulators of different thicknesses'19985,760,600'Test device for insulated-gate field effect transistor and testing circuit and testing method using the same'19985,654,236'Method for manufacturing contact structure capable of avoiding short-circuit'19975,381,030'Semiconductor memory device with improved step protection and manufacturing method thereof'19954,951,117'Isolation of insulated-gate field-effect transistors'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990–2010Patents assigned to NEC CORP (30)· patent assignee history
1990–2010Based in Tokyo, JP· patent location history
2003Patents assigned to NEC ELECTRONICS CORP (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC CORP | 30 | 1990–2010 |
| NEC ELECTRONICS CORP | 1 | 2003 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 31 | 1990–2010 |