Inventor
Masataka Takebuchi
Inventor
Yokohama, JP
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices38%
H10BElectronic memory devices35%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%
G11CStatic stores5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
PatentTitleYear
8,604,522'Field effect type semiconductor device and method for manufacturing the same'20138,034,695'Semiconductor device and method of manufacturing the same'20117,948,023'Semiconductor device including nonvolatile memory and method for fabricating the same'20117,592,667'Semiconductor device including nonvolatile memory and method for fabricating the same'20097,282,413'Semiconductor device including nonvolatile memory and method for fabricating the same'20077,023,049'Semiconductor device including nonvolatile memory'20066,900,086'Semiconductor device having MISFETs'20056,624,468'Semiconductor device including insulated gate field effect transistors'20036,417,051'Method of manufacturing memory device including insulated gate field effect transistors'20026,376,879'Semiconductor device having MISFETs'20026,078,074'Semiconductor device having multilayer metal interconnection'20006,018,195'MOS gate structure semiconductor device'20005,553,016'Semiconductor memory device'19965,532,181'Method of manufacturing semiconductor non-volatile memory device having different gate insulating thicknesses'19965,341,329'Nonvolatile semiconductor memory device capable of preventing read error caused by overerase state and method therefor'19945,324,972'Semiconductor non-volatile memory device and method of manufacturing the same'19945,190,894'Method of forming a wiring layer of a semiconductor device'19935,151,761'Nonvolatile semiconductor memory device with isolated gate electrodes'19925,138,410'Nonvolatile semiconductor memory device having tunnel insulating film structure'19925,101,248'Semiconductor device'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2013Patents assigned to TOSHIBA KK (20)· patent assignee history
1992–1996Based in Yokohama, JP· patent location history
2000–2005Based in Yokosuka, JP· patent location history
2006–2013Based in Kanagawa, JP· patent location history
2013Patents assigned to IKEDA NORIYASU (1)· patent assignee history
2013Patents assigned to TAKEBUCHI MASATAKA (1)· patent assignee history
2013Patents assigned to UTSUNOMIYA KAZUHIRO (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TOSHIBA KK | 20 | 1992–2013 |
| IKEDA NORIYASU | 1 | 2013 |
| TAKEBUCHI MASATAKAself | 1 | 2013 |
| UTSUNOMIYA KAZUHIRO | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yokohama, JP | 8 | 1992–1996 |
| Kanagawa, JP | 6 | 2006–2013 |
| Yokosuka, JP | 6 | 2000–2005 |