Inventor
Brian Michael Stempel
Inventor
Raleigh, NC, US
Overview
Patents· 45 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing88%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use12%
PatentTitleYear
11,061,822Method, apparatus, and system for reducing pipeline stalls due to address translation misses202110,956,162Operand-based reach explicit dataflow processors, and related methods and computer-readable media202110,877,895Method, apparatus, and system for prefetching exclusive cache coherence state for store instructions202010,318,436Precise invalidation of virtually tagged caches201910,108,419Dependency-prediction of instructions20189,858,077'Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable media'20189,823,929'Optimizing performance for context-dependent instructions'20179,477,478'Multi level indirect predictor using confidence counter and program counter address filter scheme'20169,477,476'Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media'20169,460,018'Method and apparatus for tracking extra data permissions in an instruction cache'20169,411,590'Method to improve speed of executing return branch instructions in a processor'20169,329,930'Cache memory error detection circuits for detecting bit flips in valid indicators in cache memory following invalidate operations, and related methods and processor-based systems'20169,317,293'Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media'20169,195,466'Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable media'20159,146,741'Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable media'20158,943,300'Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information'20158,898,437'Predecode repair cache for instructions that cross an instruction cache line'20148,819,342'Methods and apparatus for managing page crossing instructions with different cacheability'20148,438,372'Link stack repair of erroneous speculative update'20138,438,371'Link stack repair of erroneous speculative update'20138,352,713'Debug circuit comparing processor instruction set operating mode'20138,291,202'Apparatus and methods for speculative interrupt vector prefetching'20128,185,725'Selective powering of a BHT in a processor having variable length instructions'20128,145,883'Preloading instructions from an instruction set other than a currently executing instruction set'20128,082,428'Methods and system for resolving simultaneous predicted branch instructions'20117,984,279'System and method for using a working global history register'20117,971,044'Link stack repair of erroneous speculative update'20117,962,725'Pre-decoding variable length instructions'20117,917,731'Method and apparatus for prefetching non-sequential instruction addresses'20117,827,392'Sliding-window, block-based branch target address cache'20107,805,588'Caching memory attribute indicators with cached memory data field'20107,769,983'Caching instructions for a multiple-state processor'20107,716,460'Effective use of a BHT in processor having variable length instruction set execution modes'20107,711,930'Apparatus and method for decreasing the latency between instruction cache and a pipeline processor'20107,711,927'System, method and software to preload instructions from an instruction set other than one currently executing'20107,676,659'System, method and software to preload instructions from a variable-length instruction set with proper pre-decoding'20107,650,466'Method and apparatus for managing cache partitioning using a dynamic boundary'20107,617,387'Methods and system for resolving simultaneous predicted branch instructions'20097,478,228'Apparatus for generating return address predictions for implicit and explicit subroutine calls'20097,421,568'Power saving methods and apparatus to selectively enable cache bits based on known processor state'20087,415,638'Pre-decode error handling via branch correction'20087,406,613'Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions'20087,404,042'Handling cache miss in an instruction crossing a cache line boundary'20087,281,120'Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor'20077,278,012'Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2021Patents assigned to QUALCOMM INC (42)· patent assignee history
2007–2021Based in Raleigh, NC, US· patent location history
2011–2016Patents assigned to STEMPEL BRIAN MICHAEL (11)· patent assignee history
2011–2015Patents assigned to SMITH RODNEY WAYNE (8)· patent assignee history
2011–2016Patents assigned to DIEFFENDERFER JAMES NORRIS (7)· patent assignee history
2011–2015Patents assigned to SARTORIUS THOMAS ANDREW (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QUALCOMM INC | 42 | 2007–2021 |
| STEMPEL BRIAN MICHAELself | 11 | 2011–2016 |
| SMITH RODNEY WAYNE | 8 | 2011–2015 |
| DIEFFENDERFER JAMES NORRIS | 7 | 2011–2016 |
| SARTORIUS THOMAS ANDREW | 4 | 2011–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Raleigh, NC, US | 45 | 2007–2021 |