Inventor

Daniel R. Loughmiller

Inventor

Boise, ID, US

Overview

1994–2008

Patent span

Physics

Primary field (CPC G)

Patents· 42 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores46%

H03KPulse technique21%

G01RMeasuring electric variables16%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses5%

H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%

PatentTitleYear

7,468,623'Clamp circuit with fuse options'2008 7,254,753'Circuit and method for configuring CAM array margin test and operation'2007 7,196,544'Communication device for a logic circuit'2007 7,053,650'Communication device for a logic circuit'2006 6,946,863'Circuit and method for measuring and forcing an internal voltage of an integrated circuit'2005 6,901,013'Controller for delay locked loop circuits'2005 6,885,238'Clamp circuit with fuse options'2005 6,847,534'High density dynamic ternary-CAM memory architecture'2005 6,836,437'Method of reducing standby current during power down mode'2004 6,836,419'Split word line ternary CAM architecture'2004 6,822,475'Method for contact pad isolation'2004 6,809,974'Controller for delay locked loop circuits'2004 6,744,654'High density dynamic ternary-CAM memory architecture'2004 6,737,897'Power reduction for delay locked loop circuits'2004 6,665,219'Method of reducing standby current during power down mode'2003 6,628,144'Circuit and method for contact pad isolation'2003 6,586,979'Method for noise and power reduction for digital delay lines'2003 6,564,351'Circuit and method for testing an integrated circuit'2003 6,448,756'Delay line tap setting override for delay locked loop (DLL) testability'2002 6,438,060'Method of reducing standby current during power down mode'2002 6,396,300'Circuit and method for contact pad isolation'2002 6,377,089'Output driver'2002 6,351,180'Clamp circuit with fuse options'2002 6,266,794'Circuit and method for testing an integrated circuit'2001 6,229,296'Circuit and method for measuring and forcing an internal voltage of an integrated circuit'2001 6,140,831'Apparatus and methods selectively deriving a boosted voltage exceeding an internal voltage'2000 6,117,696'Circuit and method for measuring and forcing an internal voltage of an integrated circuit'2000 6,114,878'Circuit for contact pad isolation'2000 6,097,223'Drive-current modulated output driver'2000 6,088,282'System and method for an antifuse bank'2000 5,977,763'Circuit and method for measuring and forcing an internal voltage of an integrated circuit'1999 5,942,000'Circuit and method for testing an integrated circuit'1999 5,936,908'System and method for an antifuse bank'1999 5,872,740'System and method for an antifuse bank'1999 5,751,158'Method and apparatus for selectively deriving a boosted voltage exceeding an internal voltage'1998 5,742,549'Sense amplifier circuit for detecting degradation of digit lines and method thereof'1998 5,727,001'Circuit and method for testing an integrated circuit'1998 5,724,282'System and method for an antifuse bank'1998 5,629,843'Self compensating clamp circuit and method for limiting a potential at a pump circuit node'1997 5,615,158'Sense amplifier circuit for detecting degradation of digit lines and method thereof'1997 5,428,310'Voltage compensating delay element'1995 5,352,945'Voltage compensating delay element'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–1995Patents assigned to MICRON SEMICONDUCTOR INC (2)· patent assignee history

1994–2008Based in Boise, ID, US· patent location history

1997–2008Patents assigned to MICRON TECHNOLOGY INC (40)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	40	1997–2008
MICRON SEMICONDUCTOR INC	2	1994–1995

Locations

Location	Patents	Span
Boise, ID, US	42	1994–2008