Inventor
Kenneth P. Fuchs
Inventor
Colorado Springs, CO, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1065%
H10DInorganic electric semiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
PatentTitleYear
7,176,082'Analog capacitor in dual damascene process'20077,118,985'Method of forming a metal-insulator-metal capacitor in an interconnect cavity'20066,822,282'Analog capacitor in dual damascene process'20046,596,579'Method of forming analog capacitor dual damascene process'20036,522,005'Integrated circuit device comprising low dielectric constant material for reduced cross talk'20036,522,006'Low dielectric constant material in integrated circuit'20036,504,250'Integrated circuit device with reduced cross talk'20036,504,202'Interconnect-embedded metal-insulator-metal capacitor'20036,504,249'Integrated circuit device with reduced cross talk'20036,448,653'Method for using low dielectric constant material in integrated circuit fabrication'20026,358,837'Method of electrically connecting and isolating components with vertical elements extending between interconnect layers in an integrated circuit'20026,208,029'Integrated circuit device with reduced cross talk'20016,071,817'Isolation method utilizing a high pressure oxidation'20006,057,571'High aspect ratio, metal-to-metal, linear capacitor for an integrated circuit'20006,010,963'Global planarization using SOG and CMP'20005,543,361'Process for forming titanium silicide local interconnect'19965,447,880'Method for forming an amorphous silicon programmable element'19955,443,996'Process for forming titanium silicide local interconnect'19955,438,022'Method for using low dielectric constant material in integrated circuit fabrication'19955,312,512'Global planarization using SOG and CMP'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994Patents assigned to NCR CO (1)· patent assignee history
1994–2007Based in Colorado Springs, CO, US· patent location history
1995–2003Patents assigned to HYUNDAI ELECTRONICS AMERICA (11)· patent assignee history
1995–1996Patents assigned to AT & T GLOBAL INF SOLUTION (4)· patent assignee history
1996Patents assigned to SYMBIOS LOGIC INC (1)· patent assignee history
2000–2007Patents assigned to LSI LOGIC CORP (8)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HYUNDAI ELECTRONICS AMERICA | 11 | 1995–2003 |
| LSI LOGIC CORP | 8 | 2000–2007 |
| AT & T GLOBAL INF SOLUTION | 4 | 1995–1996 |
| NCR CO | 1 | 1994 |
| SYMBIOS LOGIC INC | 1 | 1996 |
Locations
| Location | Patents | Span |
|---|---|---|
| Colorado Springs, CO, US | 20 | 1994–2007 |