Inventor
Jonathon Stiff
Inventor
Beaverton, OR, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique23%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses19%
LOC0119%
H03FAmplifiers12%
G05FSystems for regulating electric or magnetic variables8%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems8%
H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner8%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications4%
PatentTitleYear
D0927821Confection2021D0927122Confection2021D0927126Confection2021D0927125Confection2021D0927123Confection202110,199,939Multi-phase DC-DC converters with open-loop PWM for transient performance enhancement201910,170,992Adaptive amplification active filter for divider-less high frequency DC-DC converters20198,085,067'Differential-to-single ended signal converter circuit and method'20117,961,060'Amplitude regulated resonant oscillator with sampled feedback'20117,893,724'Method and circuit for rapid alignment of signals'20117,518,420'Delay circuit limit detection circuit and method'20097,394,308'Circuit and method for implementing a low supply voltage current reference'20087,295,049'Method and circuit for rapid alignment of signals'20077,265,633'Open loop bandwidth test architecture and method for phase locked loop (PLL)'20077,196,586'Oscillator amplifier circuit operable to provide symmetric current limiting and method of same'20077,170,319'Method and an apparatus to reduce duty cycle distortion'20077,123,113'Regulated, symmetrical crystal oscillator circuit and method'20067,030,662'Rail-to-rail input linear voltage to current converter'20066,911,857'Current controlled delay circuit'20056,466,078'Reduced static phase error CMOS PLL charge pump'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2011Patents assigned to CYPRESS SEMICONDUCTOR CORP (13)· patent assignee history
2005–2011Based in Beaverton, OR, US· patent location history
2009–2011Based in Moscow, ID, US· patent location history
2011Patents assigned to STIFF JONATHON (1)· patent assignee history
2019Patents assigned to DIALOG SEMICONDUCTOR UK LTD (2)· patent assignee history
2019Based in Chandler, AZ, US· patent location history
2019Based in Phoenix, AZ, US· patent location history
2021Patents assigned to HERSHEY CO (5)· patent assignee history
2021Based in Falcon Heights, MN, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CYPRESS SEMICONDUCTOR CORP | 13 | 2002–2011 |
| HERSHEY CO | 5 | 2021 |
| DIALOG SEMICONDUCTOR UK LTD | 2 | 2019 |
| STIFF JONATHONself | 1 | 2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 9 | 2005–2011 |
| Falcon Heights, Minnesota, US | 5 | 2021 |
| Moscow, ID, US | 3 | 2009–2011 |
| Chandler, AZ, US | 1 | 2019 |
| Phoenix, AZ, US | 1 | 2019 |