Inventor
Takuya Ariki
Inventor
Hyogo, JP
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores44%
H01LSemiconductor devices18%
H10BElectronic memory devices18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
H10DInorganic electric semiconductor devices4%
G05FSystems for regulating electric or magnetic variables2%
H05KPrinted circuits2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
PatentTitleYear
11,081,192Memory plane structure for ultra-low read latency applications in non-volatile memories202110,991,429Word line decoder circuitry under a three-dimensional memory array202110,984,874Differential dbus scheme for low-latency random read for NAND memories202110,885,984Area effective erase voltage isolation in NAND memory202110,854,619Three-dimensional memory device containing bit line switches202010,734,080Three-dimensional memory device containing bit line switches202010,720,213Word line decoder circuitry under a three-dimensional memory array20209,721,663'Word line decoder circuitry under a three-dimensional memory array'20179,595,535'Integration of word line switches with word line contact via structures'20178,395,434'Level shifter with negative voltage capability'20138,076,911'Flash memory and related voltage regulator'20117,881,122'Discharge circuit'20117,710,793'Write voltage generating circuit and method'20106,727,584'Semiconductor module'20046,535,438'Semiconductor memory device adopting redundancy system'20036,377,512'Clock synchronous type semiconductor memory device that can switch word configuration'20026,166,989'Clock synchronous type semiconductor memory device that can switch word configuration'20006,052,316'Output buffer circuitry for semiconductor integrated circuit device'20005,986,964'Semiconductor memory device consistently operating a plurality of memory cell arrays distributed in arrangement'19995,925,141'Semiconductor memory device with data scramble circuit'19995,815,032'Semiconductor device capable of preventing fluctuations of substrate potential'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2003Patents assigned to MITSUBISHI ELECTRIC CORP (7)· patent assignee history
1998–2004Based in Hyogo, JP· patent location history
2010–2011Patents assigned to SAMSUNG ELECTRONICS CO LTD (3)· patent assignee history
2010–2020Based in Yokohama, JP· patent location history
2011–2013Patents assigned to ARIKI TAKUYA (2)· patent assignee history
2013–2017Patents assigned to SANDISK TECHNOLOGIES INC (3)· patent assignee history
2017–2021Patents assigned to SANDISK TECHNOLOGIES LLC (9)· patent assignee history
2017–2021Based in Yokkaichi, JP· patent location history
2021Based in Kanagawa, JP· patent location history
2021Based in Yokohama-shi, Kanagawa, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK TECHNOLOGIES LLC | 9 | 2017–2021 |
| MITSUBISHI ELECTRIC CORP | 7 | 1998–2003 |
| SAMSUNG ELECTRONICS CO LTD | 3 | 2010–2011 |
| SANDISK TECHNOLOGIES INC | 3 | 2013–2017 |
| ARIKI TAKUYAself | 2 | 2011–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hyogo, JP | 7 | 1998–2004 |
| Yokohama, JP | 5 | 2010–2020 |
| Yokkaichi, JP | 4 | 2017–2021 |
| Kanagawa, JP | 2 | 2021 |
| Yokohama-shi, Kanagawa, JP | 1 | 2021 |