Inventor
Brad W. Simeral
Inventor
San Francisco, CA, US
Overview
Patents· 41 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing45%
G09GArrangements or circuits for control of indicating devices using static means to present variable information16%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%
G06TImage data processing or generation, in general9%
G11CStatic stores5%
G01KMeasuring temperature2%
G01RMeasuring electric variables2%
H02JElectric power networks2%
H02KDynamo-electric machines2%
H02NElectric machines not otherwise provided for2%
PatentTitleYear
10,942,559Electronic display power management systems and methods202110,825,419Collision avoidance schemes for displays202010,224,873Voltage collection bootstrap circuit201910,002,586Compression of display data stored locally on a GPU20189,823,990'System and process for accounting for aging effects in a computing device'20179,760,150'Low-power states for a computer system with integrated baseband'20179,032,101'Chipset support for binding and migrating hardware devices among heterogeneous processing units'20159,015,446'Chipset support for non-uniform memory access among heterogeneous processing units'20158,943,584'Centralized device virtualization layer for heterogeneous processing units'20158,736,617'Hybrid graphic display'20148,692,837'Screen compression for mobile applications'20148,532,098'System and method for virtual channel communication'20138,239,938'Centralized device virtualization layer for heterogeneous processing units'20128,120,614'Screen compression for mobile applications'20128,098,254'Power savings in a computing device during video playback'20128,069,355'Data path controller with integrated power management to manage power consumption of a computing device and its components'20117,966,439'Apparatus, system, and method for a fast data return memory controller'20117,966,468'Apparatus, system, and method for fast read request transfer through clock domains'20117,876,327'Power savings in a computing device during video playback'20117,849,342'Method and system for implementing generalized system stutter'20107,813,204'Method and system for memory thermal load sharing using memory on die termination'20107,755,624'Apparatus, system, and method for Z-culling'20107,716,506'Apparatus, method, and system for dynamically selecting power down level'20107,688,325'Screen compression for mobile applications'20107,584,321'Memory address and datapath multiplexing'20097,495,985'Method and system for memory thermal load sharing using memory on die termination'20097,487,371'Data path controller with integrated power management to manage power consumption of a computing device and its components'20097,461,211'System, apparatus and method for generating nonsequential predictions to access a memory'20087,450,120'Apparatus, system, and method for Z-culling'20087,441,087'System, apparatus and method for issuing predictions from an inventory to access a memory'20087,287,202'Method and apparatus for testing a memory interface'20077,287,145'System, apparatus and method for reclaiming memory holes in memory composed of identically-sized memory devices'20077,275,143'System, apparatus and method for avoiding page conflicts by characterizing addresses in parallel with translations of memory addresses'20077,260,686'System, apparatus and method for performing look-ahead lookup on predictive information in a cache memory'20077,240,179'System, apparatus and method for reclaiming memory holes in memory composed of arbitrarily-sized memory devices'20077,206,902'System, apparatus and method for predicting accesses to a memory'20077,191,088'Method and system for memory temperature detection and thermal load management'20077,053,901'System and method for accelerating a special purpose processor'20067,054,987'Apparatus, system, and method for avoiding data writes that stall transactions in a bus interface'20066,957,298'System and method for a high bandwidth-low latency memory controller'20056,647,456'High bandwidth-low latency memory controller'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2018Patents assigned to NVIDIA CORP (37)· patent assignee history
2003–2021Based in San Francisco, CA, US· patent location history
2007Based in San Bernardino, CA, US· patent location history
2011–2018Patents assigned to SIMERAL BRAD W (9)· patent assignee history
2011–2018Patents assigned to REED DAVID G (6)· patent assignee history
2012–2018Patents assigned to BENNEBROEK KOEN (4)· patent assignee history
2012–2018Patents assigned to BHAT KARTHIK (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NVIDIA CORP | 37 | 2003–2018 |
| SIMERAL BRAD Wself | 9 | 2011–2018 |
| REED DAVID G | 6 | 2011–2018 |
| BENNEBROEK KOEN | 4 | 2012–2018 |
| BHAT KARTHIK | 4 | 2012–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Francisco, California, US | 40 | 2003–2021 |
| San Bernardino, California, US | 1 | 2007 |