Inventor

Chi-Yuan Shih

Inventor

Hsinchu, TW

Overview

2009–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 40 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices25%

H10DInorganic electric semiconductor devices25%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%

G01NInvestigating or analysing materials by determining their chemical or physical properties5%

B01DSeparation2%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%

Y10TTechnical subjects covered by former us classification2%

B81BMicrostructural devices or systems, e.g. micromechanical devices1%

B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems1%

PatentTitleYear

10,861,929Electronic device including a capacitor2020 10,535,573System and method for test key characterizing wafer processing state2020 10,381,482Passivated and faceted for fin field effect transistor2019 10,269,666System and method for test key characterizing wafer processing state2019 10,186,602Fin structure of semiconductor device2019 10,164,070Self-aligned passivation of active regions2018 10,115,597Self-aligned dual-metal silicide and germanide formation2018 10,043,908Contact structure of semiconductor device2018 10,032,889Self-aligned passivation of active regions2018 9,953,975Methods for forming STI regions in integrated circuits2018 9,680,021'Passivated and faceted fin field effect transistor'2017 9,627,280'Methods for probing semiconductor fins through four-point probe and determining carrier concentrations'2017 9,559,182'Self-aligned dual-metal silicide and germanide formation'2017 9,553,025'Selective Fin-shaping process'2017 9,530,710'Passivation structure of fin field effect transistor'2016 9,525,049'Method for fabricating fin field effect transistors'2016 9,472,652'Fin structure of semiconductor device'2016 9,455,325'Fin field-effect transistors having controlled fin height'2016 9,431,288'System and method for test key characterizing wafer processing state'2016 9,412,847'Self-aligned passivation of active regions'2016 9,379,108'Contact structure of semiconductor device'2016 9,349,659'Methods for probing semiconductor fins and determining carrier concentrations therein'2016 9,337,285'Contact structure of semiconductor device'2016 9,287,262'Passivated and faceted for fin field effect transistor'2016 9,257,343'Method for fabricating fin field effect transistors'2016 9,214,556'Self-aligned dual-metal silicide and germanide formation'2015 9,142,474'Passivation structure of fin field effect transistor'2015 9,136,383'Contact structure of semiconductor device'2015 9,093,335'Calculating carrier concentrations in semiconductor Fins using probed resistance'2015 9,048,317'Contact structure of semiconductor device'2015 9,041,158'Method of forming fin field-effect transistors having controlled fin height'2015 8,963,257'Fin field effect transistors and methods for fabricating the same'2015 8,946,829'Selective fin-shaping process using plasma doping and etching for 3-dimensional transistor applications'2015 8,721,892'Integrated chromatography devices and systems for monitoring analytes in real time and methods for manufacturing the same'2014 8,605,276'Enhanced defect scanning'2013 8,592,287'Overlay alignment mark and method of detecting overlay alignment error using the mark'2013 8,574,432'Integrated chromatography devices and systems for monitoring analytes in real time and methods for manufacturing the same'2013 8,183,701'Structure of stacking scatterometry based overlay marks for marks footprint reduction'2012 7,629,797'Resonance-induced sensitivity enhancement method for conductivity sensors'2009 7,530,259'On-chip temperature controlled liquid chromatography methods and devices'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009–2014Patents assigned to CALIFORNIA INST OF TECHN (4)· patent assignee history

2009–2014Based in Pasadena, CA, US· patent location history

2012–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (16)· patent assignee history

2012–2015Patents assigned to SHIH CHI-YUAN (8)· patent assignee history

2012–2020Based in Hsinchu, TW· patent location history

2013–2018Based in Zhubei City, TW· patent location history

2015Patents assigned to WANN CLEMENT HSINGJEN (4)· patent assignee history

2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (20)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	20	2016–2020
TAIWAN SEMICONDUCTOR MFG	16	2012–2016
SHIH CHI-YUANself	8	2012–2015
CALIFORNIA INST OF TECHN	4	2009–2014
WANN CLEMENT HSINGJEN	4	2015

Locations

Location	Patents	Span
Hsinchu, TW	34	2012–2020
Pasadena, California, US	4	2009–2014
Zhubei City, TW	2	2013–2018