Inventor

Mario Francisco Velez

Inventor

San Diego, CA, US

Overview

1995–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 104 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices20%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%

H10DInorganic electric semiconductor devices11%

H03HImpedance networks, e.g. resonant circuits11%

H01FMagnets8%

H05KPrinted circuits7%

Y10TTechnical subjects covered by former us classification4%

H04BTransmission3%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%

H01GCapacitors2%

PatentTitleYear

11,121,699Wideband filter with resonators and inductors2021 11,024,454High performance inductors2021 11,003,884Fingerprint sensor device and methods thereof2021 10,944,379Hybrid passive-on-glass (POG) acoustic filter2021 10,734,332High aspect ratio interconnects in air gap of antenna package2020 10,685,924Antenna-on-package arrangements2020 10,614,942Inductors formed with through glass vias2020 10,607,980Passive-on-glass (POG) device and method2020 10,582,609Integration of through glass via (TGV) filter and acoustic filter2020 10,553,6713D pillar inductor2020 10,523,253Glass substrate including passive-on-glass device and semiconductor die2019 10,498,307Integrated device comprising a capacitor and inductor structure comprising a shared interconnect for a capacitor and an inductor2019 10,490,348Two-dimensional structure to form an embedded three-dimensional structure2019 10,490,621Close proximity tunable inductive elements2019 10,490,880Glass-based antenna array package2019 10,433,425Three-dimensional high quality passive structure with conductive pillar technology2019 10,361,149Land grid array (LGA) packaging of passive-on-glass (POG) structure2019 10,354,795Varying thickness inductor2019 10,332,671Solenoid inductor2019 10,325,855Backside drill embedded die substrate2019 10,319,694Semiconductor assembly and method of making same2019 10,292,269Inductor with metal-insulator-metal (MIM) capacitor2019 10,290,414Substrate comprising an embedded inductor and a thin film magnetic core2019 10,249,580Stacked substrate inductor2019 10,242,957Compartment shielding in flip-chip (FC) module2019 10,187,031Tunable matching network2019 10,171,112RF multiplexer with integrated directional couplers2019 10,163,771Interposer device including at least one transistor and at least one through-substrate via2018 10,154,591Passive device assembly for accurate ground plane control2018 10,141,353Passive components implemented on a plurality of stacked insulators2018 10,141,908Multi-density MIM capacitor for improved passive on glass (POG) multiplexer performance2018 10,116,285Integration of a replica circuit and a transformer above a dielectric substrate2018 10,115,671Incorporation of passives and fine pitch through via for package on package2018 10,103,116Open-passivation ball grid array pads2018 10,103,135Backside ground plane for integrated circuit2018 10,103,703Double-sided circuit2018 10,074,625Wafer level package (WLP) ball support using cavity structure2018 10,069,474Encapsulation of acoustic resonator devices2018 10,049,815Nested through glass via transformer2018 10,044,390Glass substrate including passive-on-glass device and semiconductor die2018 10,039,188Two-stage power delivery architecture2018 10,038,422Single-chip multi-frequency film bulk acoustic-wave resonators2018 10,026,546Apparatus with 3D wirewound inductor integrated within a substrate2018 9,966,426Augmented capacitor structure for high quality (Q)-factor radio frequency (RF) applications2018 9,959,964Thin film magnet inductor structure for high quality (Q)-factor radio frequency (RF) applications2018 9,954,267Multiplexer design using a 2D passive on glass filter integrated with a 3D through glass via filter2018 9,935,166Capacitor with a dielectric between a via and a plate of the capacitor2018 9,930,783'Passive device assembly for accurate ground plane control'2018 9,906,318'Frequency multiplexer'2018 9,893,048'Passive-on-glass (POG) device and method'2018 9,876,513LC filter layer stacking by layer transfer to make 3D multiplexer structures2018 9,875,848MIM capacitor and method of making the same2018 9,813,043'Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) and related components and methods'2017 9,807,882'Density-optimized module-level inductor ground structure'2017 9,780,048'Side-assembled passive devices'2017 9,773,862'High quality factor capacitors and methods for fabricating high quality factor capacitors'2017 9,691,694'Substrate comprising stacks of interconnects, interconnect on solder resist layer and interconnect on side portion of substrate'2017 9,692,386'Three-dimensional wire bond inductor'2017 9,666,362'Superposed structure 3D orthogonal through substrate inductor'2017 9,660,110'Varactor device with backside contact'2017 9,634,640'Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) and related components and methods'2017 9,634,645'Integration of a replica circuit and a transformer above a dielectric substrate'2017 9,620,463'Radio-frequency (RF) shielding in fan-out wafer level package (FOWLP)'2017 9,560,745'Devices and methods to reduce stress in an electronic device'2017 9,548,350'High quality factor capacitors and methods for fabricating high quality factor capacitors'2017 9,536,805'Power management integrated circuit (PMIC) integration into a processor package'2017 9,496,255'Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same'2016 9,478,348'Vertical spiral inductor'2016 9,468,098'Face-up substrate integration with solder ball connection in semiconductor package'2016 9,461,614'Asymmetric unbalanced acoustically coupled resonators for spurious mode suppression'2016 9,449,753'Varying thickness inductor'2016 9,431,510'Metal-semiconductor wafer bonding for high-Q devices'2016 9,431,473'Hybrid transformer structure on semiconductor devices'2016 9,425,761'High pass filters and low pass filters using through glass via technology'2016 9,401,689'Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) and related components and methods'2016 9,384,883'Nested through glass via transformer'2016 9,379,802'Radio frequency switch for diversity receiver'2016 9,379,686'Resonator with a staggered electrode configuration'2016 9,368,566'Package on package (PoP) integrated device comprising a capacitor in a substrate'2016 9,368,564'3D pillar inductor'2016 9,370,103'Low package parasitic inductance using a thru-substrate interposer'2016 9,362,218'Integrated passive device (IPD) on substrate'2016 9,355,967'Stress compensation patterning'2016 9,343,399'Thick conductive stack plating process with fine critical dimension feature size for compact passive on glass technology'2016 9,343,403'Stress mitigation structure for wafer warpage reduction'2016 9,331,666'Composite dilation mode resonators'2016 9,331,665'Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) and related components and methods'2016 9,324,779'Toroid inductor in an integrated device'2016 9,275,786'Superposed structure 3D orthogonal through substrate inductor'2016 9,270,254'Cross-sectional dilation mode resonators and resonator-based ladder filters'2016 9,264,013'Systems for reducing magnetic coupling in integrated circuits (ICS), and related components and methods'2016 9,203,373'Diplexer design using through glass via technology'2015 9,202,789'Die package comprising die-to-wire connector and a wire-to-die connector configured to couple to a die package'2015 9,136,574'Compact 3-D coplanar transmission lines'2015 9,101,068'Two-stage power delivery architecture'2015 9,099,986'Cross-sectional dilation mode resonators'2015 9,008,602'Radio frequency switch for diversity receiver'2015 9,001,031'Complex passive design with special via implementation'2015 8,970,516'Integrated passives and power amplifier'2015 8,907,450'Metal-semiconductor wafer bonding for high-Q devices'2014 8,847,375'Microelectromechanical systems embedded in a substrate'2014 8,633,597'Thermal vias in an integrated circuit package with an embedded die'2014 7,602,050'Integrated circuit packaging'2009 5,454,270'Hermetically sealed pressure sensor and method thereof'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995Based in Phoenix, AZ, US· patent location history

2009–2021Patents assigned to QUALCOMM INC (95)· patent assignee history

2009–2021Based in San Diego, CA, US· patent location history

2014–2016Patents assigned to KIM JONGHAE (7)· patent assignee history

2014–2016Patents assigned to LO CHI SHUN (7)· patent assignee history

2014–2016Patents assigned to VELEZ MARIO FRANCISCO (6)· patent assignee history

2015–2018Patents assigned to QUALCOMM MEMS TECHNOLOGIES INC (7)· patent assignee history

2019Based in San Jose, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
QUALCOMM INC	95	2009–2021
KIM JONGHAE	7	2014–2016
LO CHI SHUN	7	2014–2016
QUALCOMM MEMS TECHNOLOGIES INC	7	2015–2018
VELEZ MARIO FRANCISCOself	6	2014–2016

Locations

Location	Patents	Span
San Diego, California, US	102	2009–2021
San Jose, California, US	1	2019
Phoenix, AZ, US	1	1995