Inventor
Rajan K. Pandey
Inventor
Bangalore, IN
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices25%
H10DInorganic electric semiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H10BElectronic memory devices8%
H10NElectric solid-state devices not otherwise provided for8%
B82YSpecific uses or applications of nanostructures6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
G11CStatic stores2%
H02HEmergency protective circuit arrangements2%
PatentTitleYear
10,366,897Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer201910,347,494Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer201910,319,596Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer201910,170,576Stable work function for narrow-pitch devices20199,984,883Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer20189,972,497Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer20189,735,250'Stable work function for narrow-pitch devices'20179,705,079'Tunable voltage margin access diodes'20179,680,096'Tunable voltage margin access diodes'20179,647,210'Tunable voltage margin access diodes'20179,627,484'Devices with multiple threshold voltages formed on a single wafer using strain in the high-K layer'20179,589,635'Semiconductor device with a stoichiometric gradient'20179,583,486'Stable work function for narrow-pitch devices'20179,508,930'Tunable voltage margin access diodes'20169,105,498'Gate strain induced work function engineering'20159,070,579'Gate strain induced work function engineering'20158,929,039'Silicon controlled rectifier (SCR) clamp including metal insulator transition (MIT) resistor'20158,450,792'Structure and fabrication method of tunnel field effect transistor with increased drive current and reduced gate induced drain leakage (GIDL)'2013Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2013–2019Patents assigned to IBM (18)· patent assignee history
2013–2015Patents assigned to BAJAJ MOHIT (3)· patent assignee history
2013–2015Patents assigned to NOWAK EDWARD J (3)· patent assignee history
2013–2015Patents assigned to PANDEY RAJAN K (3)· patent assignee history
2013–2015Patents assigned to MURALI KOTA V R M (2)· patent assignee history
2013–2019Based in Bangalore, IN· patent location history
2017–2019Based in Karnataka, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 18 | 2013–2019 |
| BAJAJ MOHIT | 3 | 2013–2015 |
| NOWAK EDWARD J | 3 | 2013–2015 |
| PANDEY RAJAN Kself | 3 | 2013–2015 |
| MURALI KOTA V R M | 2 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bangalore, IN | 15 | 2013–2019 |
| Karnataka, IN | 3 | 2017–2019 |