Inventor
Arvind Nembili Veeravalli
Inventor
Bangalore, IN
Overview
Patents· 4 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
10,114,920Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic20189,881,123'Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact'20188,255,850'Fabricating IC with NBTI path delay within timing constraints'20128,051,399'IC design flow incorporating optimal assumptions of power supply voltage drops at cells when performing timing analysis'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011–2012Patents assigned to TEXAS INSTRUMENTS INC (2)· patent assignee history
2011–2018Based in Bangalore, IN· patent location history
2012Patents assigned to JAIN PALKESH (1)· patent assignee history
2012Patents assigned to MANDAL AJOY (1)· patent assignee history
2012Patents assigned to VEERAVALLI ARVIND NEMBILI (1)· patent assignee history
2018Patents assigned to CADENCE DESIGN SYSTEMS INC (2)· patent assignee history
2018Based in Karnataka, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CADENCE DESIGN SYSTEMS INC | 2 | 2018 |
| TEXAS INSTRUMENTS INC | 2 | 2011–2012 |
| JAIN PALKESH | 1 | 2012 |
| MANDAL AJOY | 1 | 2012 |
| VEERAVALLI ARVIND NEMBILIself | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bangalore, IN | 3 | 2011–2018 |
| Karnataka, IN | 1 | 2018 |