LexDanaLexDanabeta
Inventor

Dipankar Pramanik

Inventor
Saratoga, CA, US

Overview

127→
Patents
1991–2018
Patent span
Electricity
Primary field (CPC H)

Patents· 127 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices16%
H10NElectric solid-state devices not otherwise provided for14%
H01LSemiconductor devices13%
H10DInorganic electric semiconductor devices10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
G06FElectric digital data processing8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
G11CStatic stores5%
C23CCoating metallic material5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
PatentTitleYear
9,884,123'Ligand-targeted molecules and methods thereof'20189,593,414'Hydrogenated amorphous silicon dielectric for superconducting devices'20179,472,423'Method for suppressing lattice defects in a semiconductor substrate'20169,465,897'Analysis of stress impact on transistor performance'20169,455,073'Superconducting circuits with reduced microwave absorption'20169,431,569'Zinc blende cadmium—manganese—telluride with reduced hole compensation effects and methods for forming the same'20169,343,673'Method for forming metal oxides and silicides in a memory device'20169,337,238'Photo-induced MSM stack'20169,331,276'Nonvolatile resistive memory element with an oxygen-gettering layer'20169,331,279'Creating an embedded ReRAM memory from a high-k metal gate transistor structure'20169,297,067'Fluorine passivation of dielectric for superconducting electronics'20169,292,627'System and method for modifying a data set of a photomask'20169,275,727'Multi-level memory array having resistive elements for multi-bit data storage'20169,245,941'Electrode for low-leakage devices'20169,246,092'Tunneling barrier creation in MSM stack as a selector device for non-volatile memory application'20169,240,236'Switching conditions for resistive random access memory cells'20169,224,799'Capacitors including inner and outer electrodes'20159,222,170'Deposition of rutile films with very high dielectric constant'20159,189,580'Analysis of stress impact on transistor performance'20159,177,996'Method for forming ReRAM chips operating at low operating temperatures'20159,178,011'Deposition of anisotropic dielectric layers orientationally matched to the physically separated substrate'20159,177,916'Amorphous silicon doped with fluorine for selectors of resistive random access memory cells'20159,141,737'Analysis of stress impact on transistor performance'20159,130,165'Atomic layer deposition of metal oxide materials for memory applications'20159,105,704'Method of depositing films with narrow-band conductive properties'20159,099,488'Methods to characterize an embedded interface of a CMOS gate stack'20159,082,927'Catalytic growth of Josephson junction tunnel barrier'20159,076,523'Methods of manufacturing embedded bipolar switching resistive memory'20159,054,032'Creating an embedded ReRAM memory from a high-k metal gate transistor structure'20159,054,307'Resistive random access memory cells having metal alloy current limiting layers'20159,025,360'Method for improving data retention of ReRAM chips operating at low operating temperatures'20159,023,739'Site-isolated rapid thermal processing methods and apparatus'20159,019,744'Barrier design for steering elements'20159,012,260'Controlling ReRam forming voltage with doping'20159,000,407'ReRAM materials stack for low-operating-power and high-density applications'20158,995,166'Multi-level memory array having resistive elements for multi-bit data storage'20158,987,865'Memory device having an integrated two-terminal current limiting resistor'20158,981,332'Nonvolatile resistive memory element with an oxygen-gettering layer'20158,975,727'Memory cell having an integrated two-terminal current limiting resistor'20158,975,114'Method for forming metal oxides and silicides in a memory device'20158,975,134'Fullerene-based capacitor electrode'20158,921,181'Flourine-stabilized interface'20148,912,518'Resistive random access memory cells having doped current limiting layers'20148,907,313'Controlling ReRam forming voltage with doping'20148,907,314'MoOx-based resistance switching materials'20148,906,736'Multifunctional electrode'20148,895,390'Memory device with a textured lowered electrode'20148,883,655'Atomic layer deposition of metal oxide materials for memory applications'20148,881,073'Analysis of stress impact on transistor performance'20148,878,152'Nonvolatile resistive memory element with an integrated oxygen isolation structure'20148,871,601'Diffusion barriers'20148,859,328'Multifunctional electrode'20148,859,093'Low-emissivity coatings'20148,854,067'Circular transmission line methods compatible with combinatorial processing of semiconductors'20148,835,310'Two step deposition of molybdenum dioxide electrode for high quality dielectric stacks'20148,817,524'Resistive random access memory cells having metal alloy current limiting layers'20148,803,124'Creating an embedded reram memory from a high-K metal gate transistor structure'20148,779,407'Multifunctional electrode'20148,778,811'Low temperature migration enhanced Si-Ge epitaxy with plasma assisted surface activation'20148,766,404'Device design for partially oriented rutile dielectrics'20148,762,924'Analysis of stress impact on transistor performance'20148,748,237'Memory device having an integrated two-terminal current limiting resistor'20148,735,217'Multifunctional electrode'20148,713,510'Analysis of stress impact on transistor performance'20148,694,942'Filler cells for design optimization in a place-and-route system'20148,686,512'Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance'20148,661,398'Analysis of stress impact on transistor performance'20148,637,413'Nonvolatile resistive memory element with a passivated switching layer'20148,615,728'Analysis of stress impact on transistor performance'20138,598,682'Memory device having an integrated two-terminal current limiting resistor'20138,572,517'System and method for modifying a data set of a photomask'20138,563,366'Memory device having an integrated two-terminal current limiting resistor'20138,560,995'Analysis of stress impact on transistor performance'20138,546,275'Atomic layer deposition of hafnium and zirconium oxides for memory applications'20138,504,969'Filler cells for design optimization in a place-and-route system'20138,466,446'Atomic layer deposition of metal oxide materials for memory applications'20138,466,005'Method for forming metal oxides and silicides in a memory device'20138,426,270'Memory device with a textured lowered electrode'20138,413,096'Analysis of stress impact on transistor performance'20138,407,634'Analysis of stress impact on transistor performance'20138,347,252'Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array'20138,288,297'Atomic layer deposition of metal oxide materials for memory applications'20128,219,961'Method for compensation of process-induced performance variation in a MOSFET integrated circuit'20128,086,990'Method of correlating silicon stress to device instance parameters for circuit simulation'20118,069,430'Stress-managed revision of integrated circuit layouts'20118,035,168'Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance'20117,949,985'Method for compensation of process-induced performance variation in a MOSFET integrated circuit'20117,897,479'Managing integrated circuit stress using dummy diffusion regions'20117,895,548'Filler cells for design optimization in a place-and-route system'20117,863,146'Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance'20117,767,515'Managing integrated circuit stress using stress adjustment trenches'20107,739,095'Method for determining best and worst cases for interconnects in timing analysis'20107,705,406'Transistor array with selected subset having suppressed layout sensitivity of threshold voltage'20107,691,693'Method for suppressing layout sensitivity of threshold voltage in a transistor array'20107,600,207'Stress-managed revision of integrated circuit layouts'20097,584,438'Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array'20097,543,254'Method and apparatus for fast identification of high stress regions in integrated circuit structure'20097,542,891'Method of correlating silicon stress to device instance parameters for circuit simulation'20097,484,198'Managing integrated circuit stress using dummy diffusion regions'20096,931,617'Mask cost driven logic optimization and synthesis'20056,928,635'Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits'20056,414,542'Integrated circuit with relative sense inversion of signals along adjacent parallel signal paths'20026,316,834'Tungsten plugs for integrated circuits and method for making same'20016,313,542'Method and apparatus for detecting edges under an opaque layer'20016,229,685'Thin capacitive structures and methods for making the same'20016,176,983'Methods of forming a semiconductor device'2001RE036893'Anti-fuse structure for reducing contamination of the anti-fuse material'20005,990,561'Tungsten plugs for integrated circuits and methods for making same'19995,852,497'Method and apparatus for detecting edges under an opaque layer'19985,834,356'Method of making high resistive structures in salicided process semiconductor devices'19985,811,346'Silicon corner rounding in shallow trench isolation process'19985,804,502'Tungsten plugs for integrated circuits and methods for making same'19985,763,937'Device reliability of MOS devices using silicon rich plasma oxide films'19985,602,056'Method for forming reliable MOS devices using silicon rich plasma oxide film'19975,573,970'Method for reducing contamination of anti-fuse material in an anti-fuse structure'19965,522,957'Method for leak detection in etching chambers'19965,496,774'Method improving integrated circuit planarization during etchback'19965,492,865'Method of making structure for suppression of field inversion caused by charge build-up in the dielectric'19965,493,146'Anti-fuse structure for reducing contamination of the anti-fuse material'19965,436,410'Method and structure for suppressing stress-induced defects in integrated circuit conductive lines'19955,403,780'Method enhancing planarization etchback margin, reliability, and stability of a semiconductor device'19955,399,533'Method improving integrated circuit planarization during etchback'19955,374,833'Structure for suppression of field inversion caused by charge build-up in the dielectric'19945,332,868'Method and structure for suppressing stress-induced defects in integrated circuit conductive lines'19945,290,727'Method for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistors'19945,128,279'Charge neutralization using silicon-enriched oxide layer'19925,057,897'Charge neutralization using silicon-enriched oxide layer'1991

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1991Based in Union City, CA, US· patent location history
1992–1998Based in Cupertino, CA, US· patent location history
1996–2017Based in Saratoga, CA, US· patent location history
2005–2016Patents assigned to SYNOPSYS INC (35)· patent assignee history
2011–2016Patents assigned to PRAMANIK DIPANKAR (28)· patent assignee history
2012–2017Patents assigned to INTERMOLECULAR INC (61)· patent assignee history
2013–2016Patents assigned to SANDISK 3D LLC (22)· patent assignee history
2013–2016Patents assigned to TOSHIBA KK (22)· patent assignee history
2018Based in Delhi, IN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTERMOLECULAR INC612012–2017
SYNOPSYS INC352005–2016
PRAMANIK DIPANKARself282011–2016
SANDISK 3D LLC222013–2016
TOSHIBA KK222013–2016
Locations
LocationPatentsSpan
Saratoga, California, US1141996–2017
Cupertino, California, US111992–1998
Delhi, IN12018
Union City, California, US11991