Inventor

Luigi Colombo

Inventor

Dallas, TX, US

Overview

1977–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 117 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices31%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%

H01LSemiconductor devices10%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%

H10BElectronic memory devices6%

B82YSpecific uses or applications of nanostructures3%

C01BNon-metallic elements3%

C23CCoating metallic material3%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

A61KPreparations for medical, dental or toiletry purposes1%

PatentTitleYear

11,081,593Integration of graphene and boron nitride hetero-structure device2021 11,063,120Metal-graphene structures forming a lattice of interconnected segments2021 11,004,680Semiconductor device package thermal conduit2021 10,964,778Precision capacitor2021 10,923,567Graphene FET with graphitic interface layer at contacts2021 10,861,763Thermal routing trench by additive processing2020 10,811,334Integrated circuit nanoparticle thermal routing structure in interconnect region2020 10,804,201Dissimilar material interface having lattices2020 10,790,228Interconnect via with grown graphitic material2020 10,748,999Multi-super lattice for switchable arrays2020 10,644,098Precision capacitor2020 10,593,763Graphene FET with graphitic interface layer at contacts2020 10,529,641Integrated circuit nanoparticle thermal routing structure over interconnect region2020 10,490,673Integration of graphene and boron nitride hetero-structure device2019 10,468,324Integration of heat spreader for beol thermal management2019 10,304,967Integration of graphene and boron nitride hetero-structure device over semiconductor layer2019 10,256,188Interconnect via with grown graphitic material2019 10,181,521Graphene heterolayers for electronic applications2019 10,181,516Graphene FET with graphitic interface layer at contacts2019 10,072,355Methods of forming graphene single crystal domains on a low nucleation site density substrate2018 10,069,065Low noise graphene hall sensors, systems and methods of making and using same2018 10,001,529Low-offset Graphene Hall sensor2018 9,882,008'Graphene FET with graphitic interface layer at contacts'2018 9,793,214'Heterostructure interconnects for high frequency applications'2017 9,698,075'Integration of backside heat spreader for thermal management'2017 9,517,938'Applying spatial gradient magnetic field to metallic/semiconducting SWNTs in fluid'2016 9,496,198'Integration of backside heat spreader for thermal management'2016 9,397,023'Integration of heat spreader for beol thermal management'2016 9,114,995'Separating Metallic and Semiconductor SWNTS with sinusoidal dipole-inducing magnetic fields'2015 8,800,077'Pull down bed with automatic locking device'2014 8,789,705'Separating metallic and semiconductor SWNTs with varying dipole-inducing magnetic fields'2014 8,753,924'Grown carbon nanotube die attach structures, articles, devices, and processes for making them'2014 8,575,014'Semiconductor device fabricated using a metal microstructure control process'2013 8,470,400'Graphene synthesis by chemical vapor deposition'2013 8,461,028'Synthesizing graphene from metal-carbon solutions using ion implantation'2013 8,309,438'Synthesizing graphene from metal-carbon solutions using ion implantation'2012 8,198,184'Method to maximize nitrogen concentration at the top surface of gate dielectrics'2012 8,198,707'Establishing a uniformly thin dielectric layer on graphene in a semiconductor device without affecting the properties of graphene'2012 8,143,212'Dalbavancin compositions for treatment of bacterial infections'2012 8,124,529'Semiconductor device fabricated using a metal microstructure control process'2012 8,021,990'Gate structure and method'2011 7,842,567'Dual work function CMOS devices utilizing carbide based electrodes'2010 7,799,668'Formation of uniform silicate gate dielectrics'2010 7,642,146'Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials'2010 7,612,422'Structure for dual work function metal gate electrodes by control of interface dipoles'2009 7,601,578'Defect control in gate dielectrics'2009 7,601,577'Work function control of metals'2009 7,535,066'Gate structure and method'2009 7,531,400'Methods for fabricating MOS transistor gates with doped silicide'2009 7,528,024'Dual work function metal gate integration in semiconductor devices'2009 7,470,577'Dual work function CMOS devices utilizing carbide based electrodes'2008 7,449,385'Gate dielectric and method'2008 7,423,326'Integrated circuits with composite gate dielectric'2008 7,387,956'Refractory metal-based electrodes for work function setting in semiconductor devices'2008 7,361,599'Integrated circuit and method'2008 7,351,626'Method for controlling defects in gate dielectrics'2008 7,351,632'Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS silicon oxynitride dielectric formation using direct nitridation of silicon'2008 7,338,865'Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation'2008 7,321,154'Refractory metal-based electrodes for work function setting in semiconductor devices'2008 7,291,890'Gate dielectric and method'2007 7,291,527'Work function control of metals'2007 7,233,035'Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound'2007 7,229,873'Process for manufacturing dual work function metal gates in a microelectronics device'2007 7,226,830'Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation'2007 7,226,826'Semiconductor device having multiple work functions and method of manufacture therefor'2007 7,183,221'Method of fabricating a semiconductor having dual gate electrodes using a composition-altered metal layer'2007 7,176,076'Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials'2007 7,163,877'Method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing'2007 7,148,546'MOS transistor gates with doped silicide and methods for making the same'2006 7,135,361'Method for fabricating transistor gate structures and gate dielectrics thereof'2006 7,115,530'Top surface roughness reduction of high-k dielectric materials using plasma based processes'2006 7,109,077'Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound'2006 7,105,891'Gate structure and method'2006 7,098,516'Refractory metal-based electrodes for work function setting in semiconductor devices'2006 7,091,119'Encapsulated MOS transistor gate structures and methods for making the same'2006 7,071,519'Control of high-k gate dielectric film composition profile for property optimization'2006 7,067,434'Hydrogen free integration of high-k gate dielectrics'2006 7,045,431'Method for integrating high-k dielectrics in transistor devices'2006 7,045,456'MOS transistor gates with thin lower metal silicide and methods for making the same'2006 7,018,902'Gate dielectric and method'2006 7,015,088'High-K gate dielectric defect gettering using dopants'2006 7,015,534'Encapsulated MOS transistor gate structures and methods for making the same'2006 6,979,623'Method for fabricating split gate transistor device having high-k dielectrics'2005 6,936,508'Metal gate MOS transistors and methods for making the same'2005 6,919,251'Gate dielectric and method'2005 6,902,939'Integrated circuit and method'2005 6,876,021'Use of amorphous aluminum oxide on a capacitor sidewall for use as a hydrogen barrier'2005 6,852,645'High temperature interface layer growth for high-k gate dielectric'2005 6,828,200'Multistage deposition that incorporates nitrogen via an intermediate step'2004 6,828,161'Method of forming an FeRAM having a multi-layer hard mask and patterning thereof'2004 6,821,873'Anneal sequence for high- film property optimization'2004 6,809,370'High-k gate dielectric with uniform nitrogen profile and methods for making the same'2004 6,797,599'Gate structure and method'2004 6,783,997'Gate structure and method'2004 6,770,521'Method of making multiple work function gates by implanting metals with metallic alloying additives'2004 6,750,126'Methods for sputter deposition of high-k dielectric films'2004 6,709,875'Contamination control for embedded ferroelectric device fabrication processes'2004 6,696,332'Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing'2004 6,635,528'Method of planarizing a conductive plug situated under a ferroelectric capacitor'2003 6,635,498'Method of patterning a FeRAM capacitor with a sidewall during bottom electrode etch'2003 6,600,183'Integrated circuit capacitor and memory'2003 6,576,546'Method of enhancing adhesion of a conductive barrier layer to an underlying conductive plug and contact for ferroelectric applications'2003 6,548,343'Method of fabricating a ferroelectric memory cell'2003 6,544,906'Annealing of high-k dielectric materials'2003 6,534,809'Hardmask designs for dry etching FeRAM capacitor stacks'2003 6,528,386'Protection of tungsten alignment mark for FeRAM processing'2003 6,444,542'Integrated circuit and method'2002 6,211,034'Metal patterning with adhesive hardmask layer'2001 6,211,035'Integrated circuit and method'2001 5,972,722'Adhesion promoting sacrificial etch stop layer in advanced capacitor structures'1999 5,959,299'Uncooled infrared sensors for the detection and identification of chemical products of combustion'1999 5,618,724'Antibiotics GE 37468 A, B and C'1997 5,610,143'Antibiotics GE 37468 A, B and C'1997 5,514,649'Antibiotic GE 2270 factors C.sub.2a'1996 4,582,683'(Hg,Cd,Zn)Te crystal compositions'1986 4,039,317'Process for the preparation of silver powder'1977 4,025,611'Process for obtaining hyperfine magnetite powder'1977

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1977Based in Arona, IT· patent location history

1986–2021Patents assigned to TEXAS INSTRUMENTS INC (107)· patent assignee history

1986Based in Richardson, TX, US· patent location history

1996–1997Patents assigned to LEPETIT SPA (3)· patent assignee history

1996–2012Based in Malnate, IT· patent location history

1999–2021Based in Dallas, TX, US· patent location history

2003–2004Patents assigned to AGILENT TECHNOLOGIES INC (5)· patent assignee history

2012–2014Patents assigned to COLOMBO LUIGI (10)· patent assignee history

2012–2018Patents assigned to UNIV TEXAS (5)· patent assignee history

2014Based in Milan, IT· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TEXAS INSTRUMENTS INC	107	1986–2021
COLOMBO LUIGIself	10	2012–2014
AGILENT TECHNOLOGIES INC	5	2003–2004
UNIV TEXAS	5	2012–2018
LEPETIT SPA	3	1996–1997

Locations

Location	Patents	Span
Dallas, Texas, US	109	1999–2021
Malnate, IT	4	1996–2012
Arona, IT	2	1977
Milan, IT	1	2014
Richardson, Texas, US	1	1986