Inventor
Hiromi Nobukata
Inventor
Kanagawa, JP
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores46%
H10DInorganic electric semiconductor devices18%
H10BElectronic memory devices13%
G06FElectric digital data processing8%
H04LTransmission of digital information, e.g. telegraphic communication8%
G06KGraphical data reading5%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy3%
PatentTitleYear
8,843,763'Integrated circuit and electronic apparatus'20148,370,642'Cryptographic processing apparatus'20138,350,574'Circuit for detecting malfunction generation attack and integrated circuit using the same'20138,213,603'Encryption processing apparatus'20127,450,451'Nonvolatile memory system and method for controlling nonvolatile memory'20087,145,808'Nonvolatile semiconductor memory apparatus and method of producing the same'20067,142,451'Nonvolatile semiconductor memory apparatus and method of producing the same'20067,102,931'Nonvolatile semiconductor memory apparatus and method of producing the same'20067,088,622'Nonvolatile semiconductor memory apparatus and method of producing the same'20066,903,977'Nonvolatile semiconductor memory device and method of producing the same'20056,581,843'Record medium and data transferring method using nonvolatile memory'20036,266,270'Non-volatile semiconductor memory and programming method of the same'20016,259,624'Nonvolatile semiconductor storage device and data writing method thereof'20016,128,229'Non-volatile semiconductor memory and method of verifying after writing and reading the same'20006,058,042'Semiconductor nonvolatile memory device and method of data programming the same'20006,046,933'Nonvolatile semiconductor memory device and IC memory card using same'20005,991,195'Flash EEPROM with erase verification and address scrambling architecture'19995,909,395'Flash EEPROM with erase verification and address scrambling architecture'19995,894,435'Nonvolatile semiconductor memory device and method of reducing read disturbance'19995,822,248'Non-volatile semiconductor memory device using folded bit line architecture'19985,524,094'Nonvolatile memory device with NAND array'19965,521,868'NOR-type non-volatile memory using tunnel current and having selective re-write'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2014Patents assigned to SONY CORP (22)· patent assignee history
1996–2014Based in Kanagawa, JP· patent location history
1999Based in Tokyo, JP· patent location history
2012–2014Patents assigned to NOBUKATA HIROMI (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SONY CORP | 22 | 1996–2014 |
| NOBUKATA HIROMIself | 4 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kanagawa, JP | 21 | 1996–2014 |
| Tokyo, JP | 1 | 1999 |