Inventor
Trung N. Nguyen
Inventor
Tucson, AZ, US
Overview
Patents· 64 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing79%
H04LTransmission of digital information, e.g. telegraphic communication9%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
F41GWeapon sights3%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems1%
PatentTitleYear
10,831,559Processor thread management202010,810,304Injecting trap code in an execution path of a process executing a program to generate a trap address range to detect potential malicious code202010,740,030Stopping a plurality of central processing units for data collection based on attributes of tasks202010,733,025Balancing categorized task queues in a plurality of processing entities of a computational device202010,691,502Task queuing and dispatching mechanisms in a computational device202010,671,438Providing additional memory and cache for the execution of critical tasks by folding processing units of a processor complex202010,642,755Invoking demote threads on processors to demote tracks from a cache based on free cache segments202010,606,714Stopping central processing units for data collection based on event categories of events202010,579,413Efficient task scheduling using a locking mechanism202010,565,020Adjustment of the number of central processing units to meet performance requirements of an I/O resource202010,545,795Determination of memory access patterns of tasks in a multi-core processor202010,540,170Concurrent I/O enclosure firmware/field-programmable gate array (FPGA) update in a multi-node environment202010,528,412Multiple path error data collection in a storage management system202010,528,437Monitoring correctable errors on a bus interface to determine whether to redirect input/output request (I/O) traffic to another bus interface202010,430,264Monitoring correctable errors on a bus interface to determine whether to redirect input/output (I/O) traffic from a first processing unit to a second processing unit201910,394,713Selecting resources to make available in local queues for processors to use201910,387,218Lock profiling tool to identify code bottlenecks in a storage controller201910,379,943Management of foreground and background processes in a storage controller201910,346,317Determining cores to assign to cache hostile tasks201910,318,156Invoking input/output (I/O) threads on processors to demote tracks from a cache201910,275,280Reserving a core of a processor complex for a critical task201910,255,117Task queuing and dispatching mechanisms in a computational device201910,255,223Detecting a type of storage adapter connected and miscabling of a microbay housing the storage adapter201910,248,457Providing exclusive use of cache associated with a processing entity of a processor complex to a selected task201910,248,464Providing additional memory and cache for the execution of critical tasks by folding processing units of a processor complex201910,228,985Adjustment of a sleep duration for a process based on an expected time for securing a spinlock201910,223,164Execution of critical tasks based on the number of available processing entities201910,204,060Determining memory access categories to use to assign tasks to processor cores to execute201910,185,593Balancing categorized task queues in a plurality of processing entities of a computational device201910,176,101Allocate a segment of a buffer to each of a plurality of threads to use for writing data201910,169,248Determining cores to assign to cache hostile tasks201910,157,082Preferential CPU utilization for tasks201810,120,716Task pooling and work affinity in data processing201810,114,633Concurrent I/O enclosure firmware/field-programmable gate array (FPGA) update in a multi-node environment201810,097,484Using send buffers and receive buffers for sending messages among nodes in a network201810,082,958Invoking input/output (I/O) threads on processors to demote tracks from a cache20189,971,689Invoking input/output (I/O) threads and demote threads on processors to demote tracks from a cache20189,971,508Invoking input/output (I/O) threads on processors to demote tracks from a cache20189,952,982Invoking demote threads on processors to demote tracks indicated in demote ready lists from a cache when a number of free cache segments in the cache is below a free cache segment threshold20189,886,070'Method, system, and computer program product for taking an I/O enclosure offline'20189,870,275'Processor thread management'20189,852,075Allocate a segment of a buffer to each of a plurality of threads to use for writing data20179,842,016'Multiple path error data collection in a storage management system'20179,842,010'Adjustment of a sleep duration for a process based on an expected time for securing a spinlock'20179,798,466'Using a plurality of sub-buffers and a free segment list to allocate segments to a plurality of threads to use for writing data'20179,772,785'Controlling partner partitions in a clustered storage system'20179,766,982'Preferential allocation of processors for statesave in a storage controller'20179,753,773'Performance-based multi-mode task dispatching in a multi-processor core system for extreme temperature avoidance'20179,747,139'Performance-based multi-mode task dispatching in a multi-processor core system for high temperature avoidance'20179,747,210'Managing a lock to a resource shared among a plurality of processors'20179,606,835'Determination of memory access patterns of tasks in a multi-core processor'20179,571,578'Utilization based multi-buffer self-calibrated dynamic adjustment management'20179,483,410'Utilization based multi-buffer dynamic adjustment management'20169,442,674'Using a plurality of sub-buffers and a free segment list to allocate segments to a plurality of threads to use for writing data'20169,400,676'Preferential CPU utilization for tasks'20169,396,017'Preferential CPU utilization for tasks'20169,354,945'Managing a lock to a resource shared among a plurality of processors'20169,342,249'Controlling partner partitions in a clustered storage system'20169,063,786'Preferential CPU utilization for tasks'20159,058,217'Preferential CPU utilization for tasks'20158,055,934'Error routing in a multi-root communication fabric'20117,549,090'Autonomic recovery from hardware errors in an input/output fabric'20097,134,052'Autonomic recovery from hardware errors in an input/output fabric'20066,028,777'High frequency power supply generator'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000Patents assigned to BETEK MANUFACTURING INC (1)· patent assignee history
2000Based in Sunnyvale, CA, US· patent location history
2006–2020Patents assigned to IBM (62)· patent assignee history
2006–2009Based in Rochester, MN, US· patent location history
2011–2020Based in Tucson, AZ, US· patent location history
2015Patents assigned to ASH KEVIN JOHN (1)· patent assignee history
2015Patents assigned to BENHASE MICHAEL THOMAS (1)· patent assignee history
2015Patents assigned to GUPTA LOKESH MOHAN (1)· patent assignee history
2018–2020Based in Vail, AZ, US· patent location history
2018Based in Tuscon, AZ, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 62 | 2006–2020 |
| ASH KEVIN JOHN | 1 | 2015 |
| BENHASE MICHAEL THOMAS | 1 | 2015 |
| BETEK MANUFACTURING INC | 1 | 2000 |
| GUPTA LOKESH MOHAN | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tucson, AZ, US | 48 | 2011–2020 |
| Vail, AZ, US | 12 | 2018–2020 |
| Rochester, Minnesota, US | 2 | 2006–2009 |
| Tuscon, AZ, US | 1 | 2018 |
| Sunnyvale, California, US | 1 | 2000 |