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Inventor

Brian S. Schieck

Inventor
Hayward, CA, US

Overview

7→
Patents
2010–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 7 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1032%
H01LSemiconductor devices23%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
G01RMeasuring electric variables14%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests14%
PatentTitleYear
10,943,882IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures202110,032,692Semiconductor package structure20189,831,225Low-impedance power delivery for a packaged die20179,190,396'Low-impedance power delivery for a packaged die'20158,951,814'Method of fabricating a flip chip semiconductor die with internal signal access'20158,357,931'Flip chip semiconductor die internal signal access system and method'20137,842,948'Flip chip semiconductor die internal signal access system and method'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2021Patents assigned to NVIDIA CORP (7)· patent assignee history
2010–2018Based in Hayward, CA, US· patent location history
2013–2015Patents assigned to SCHIECK BRIAN S (2)· patent assignee history
2013Patents assigned to MARKS HOWARD LEE (1)· patent assignee history
2015Patents assigned to TEMPLETON DONALD E (1)· patent assignee history
2021Based in Santa Clara, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
NVIDIA CORP72010–2021
SCHIECK BRIAN Sself22013–2015
MARKS HOWARD LEE12013
TEMPLETON DONALD E12015
Locations
LocationPatentsSpan
Hayward, California, US62010–2018
Santa Clara, California, US12021