Inventor
Bi-Ling Chen
Inventor
Taipei, TW
Overview
Patents· 15 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1038%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
H10BElectronic memory devices19%
H10DInorganic electric semiconductor devices6%
F21VFunctional features or details of lighting devices or systems thereof3%
F21YIndexing scheme associated with subclasses f21k, f21l, f21s and f21v, relating to the form or the kind of the light sources or of the colour of the light emitted3%
G02BOptical elements, systems or apparatus3%
H10HInorganic light-emitting semiconductor devices having potential barriers3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
10,989,390Folded optics methods and apparatus for improving efficiency of LED-based luminaires20216,670,279'Method of forming shallow trench isolation with rounded corners and divot-free by using in-situ formed spacers'20036,565,759'Etching process'20036,476,488'Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections'20026,245,656'Method for producing multi-level contacts'20016,239,011'Method of self-aligned contact hole etching by fluorine-containing discharges'20016,184,081'Method of fabricating a capacitor under bit line DRAM structure using contact hole liners'20016,159,839'Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections'20006,140,240'Method for eliminating CMP induced microscratches'20006,103,588'Method of forming a contact hole in a semiconductor device'20006,080,662'Method for forming multi-level contacts using a H-containing fluorocarbon chemistry'20006,074,952'Method for forming multi-level contacts'20006,037,211'Method of fabricating contact holes in high density integrated circuits using polysilicon landing plug and self-aligned etching processes'20006,025,255'Two-step etching process for forming self-aligned contacts'20005,956,594'Method for simultaneously forming capacitor plate and metal contact structures for a high density DRAM device'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2003Patents assigned to VANGUARD INT SEMICONDUCT CORP (13)· patent assignee history
1999–2003Based in Taipei, TW· patent location history
2003Patents assigned to TAIWAN SEMICONDUCTOR MFG (1)· patent assignee history
2021Patents assigned to DMF INC (1)· patent assignee history
2021Based in Lomita, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| VANGUARD INT SEMICONDUCT CORP | 13 | 1999–2003 |
| DMF INC | 1 | 2021 |
| TAIWAN SEMICONDUCTOR MFG | 1 | 2003 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taipei, TW | 14 | 1999–2003 |
| Lomita, California, US | 1 | 2021 |