Inventor
Sherry R. Taft
Inventor
Sherwood, OR, US
Overview
Patents· 5 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices33%
H10DInorganic electric semiconductor devices33%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
PatentTitleYear
10,249,742Offstate parasitic leakage reduction for tunneling field effect transistors201910,204,989Method of fabricating semiconductor structures on dissimilar substrates201910,096,682III-N devices in Si trenches20189,698,222'Method of fabricating semiconductor structures on dissimilar substrates'20179,640,422'III-N devices in Si trenches'2017Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2017–2019Patents assigned to INTEL CORP (5)· patent assignee history
2017–2019Based in Sherwood, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 5 | 2017–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sherwood, OR, US | 5 | 2017–2019 |